# US 2018/0025790 A1 · Redundant column or row in resistive random access memory

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- Number: US 2018/0025790 A1
- Document ID: US20180025790A1
- Status: Published application
- Kind: A1
- Application number: 15/216,589
- Filed: 2016-07-21
- Published: 2018-01-25
- Earliest claimed: 2016-07-21
- Assignees: Hewlett Packard Enterprise Development LP
- Applicants: Hewlett Packard Enterprise Development LP
- Inventors: Emmanuelle J. Merced Grafals; Brent Buchanan; Le Zheng
- Web page: https://patentgrep.com/patent/US20180025790A1

## CPC

- G11C 29/789: {using non-volatile cells or latches}
- G11C 13/0021: {Auxiliary circuits}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/20: Multistable switching devices, e.g. memristors
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

Examples include a resistive random access memory (RRAM) array to support a redundant column. Some examples include an RRAM cell at a cross point of a column line and a row line of the RRAM array. A first column line may be coupled to a first input of a first current-steering multiplexer and the first current-steering multiplexer may have an output coupled to a first current sense amplifier and a select input coupled to a first column select signal. A second column line may be coupled to a second input of the first current-steering multiplexer and coupled to a first input of a second current-steering multiplexer. The second current-steering multiplexer may have an output coupled to a second current sense amplifier and a select input coupled to a second column select signal. A third column line may be coupled to a second input of the second current-steering multiplexer.

## Claims

### Claim 1

A resistive random access memory (RRAM) array to support a redundant column comprising:
an RRAM cell at a cross point of a column line and a row line;
a first column line coupled to a first input of a first current-steering multiplexer, wherein the first current-steering multiplexer has an output coupled to a first current sense amplifier and a select input coupled to a first column select signal;
a second column line coupled to a second input of the first current-steering multiplexer and coupled to a first input of a second current-steering multiplexer, wherein the second current-steering multiplexer has an output coupled to a second current sense amplifier and a select input coupled to a second column select signal; and
a third column line coupled to a second input of the second current-steering multiplexer;
wherein when one of the column lines has failed, the RRAM array to apply a low column select signal to one of the current-steering multiplexers and a high column select signal to another of the current-steering multiplexers to avoid the failed column line.

### Claim 2 (depends on 1)

The RRAM array of claim 1, wherein each RRAM cell is bipolar.

### Claim 3 (depends on 2)

The RRAM array of claim 2, wherein the first and second current-steering multiplexers each further comprises a first n-channel field-effect transistor (nFET) and a second nFET.

### Claim 4 (depends on 2)

The RRAM array of claim 2, wherein the first and second current-steering multiplexers each further comprises a first full pass gate and a second full pass gate.

### Claim 5 (depends on 1)

The RRAM array of claim 1, wherein each RRAM cell is unipolar.

### Claim 6 (depends on 5)

The RRAM array of claim 5, wherein the first and second current-steering multiplexers each further comprises a first p-channel field-effect transistor (pFET) and a second pFET.

### Claim 7 (depends on 3)

The RRAM array of claim 3, wherein the second column line has failed and wherein the first column select signal is set low and the second column select signal is set high to avoid the failed second column line.

### Claim 8 (depends on 1)

The RRAM array of claim 1, wherein the first, second, and third column lines support a single-ended analog current signal.

### Claim 9

A resistive random access memory (RRAM) array to support a redundant row comprising:
a plurality of row lines;
a plurality of column lines perpendicular to the plurality of row lines, wherein a cross point is formed at each location where a row line of the plurality of row lines crosses a column line of the plurality of column lines;
an RRAM cell at each cross point;
a plurality of switches coupled to the plurality of row lines, wherein a first row line of the plurality of row lines is coupled to a first switch of the plurality of switches, a last row line of the plurality of row lines is coupled to a last switch of the plurality of switches, and each of a remainder of row lines of the plurality of row lines is coupled to two switches of the plurality of switches;
a plurality of row select signals, wherein each switch of the plurality of switches is coupled to a row select signal of the plurality of row select signals; and
a plurality of drivers, wherein each switch is coupled to a driver.

### Claim 10 (depends on 9)

The RRAM array of claim 9, wherein the plurality of switches are current-steering multiplexers, each row line of the plurality of row lines supports a single-ended analog current signal, and the plurality of drivers are current drivers.

### Claim 11 (depends on 9)

The RRAM array of claim 9, wherein the plurality of switches are voltage multiplexers, each row line of the plurality of row lines supports a single-ended analog voltage signal, and the plurality of drivers are voltage drivers.

### Claim 12 (depends on 11)

The RRAM array of claim 11, further comprising:
a plurality of current-steering multiplexers to support a redundant column that are coupled to the plurality of column lines, wherein a first column line of the plurality of column lines is coupled to a first current-steering multiplexer of the plurality of current-steering multiplexers, a last column line of the plurality of column lines is coupled to a last current-steering multiplexer of the plurality of current-steering multiplexers, and each of a remainder of column lines of the plurality of column lines is coupled to two current-steering multiplexers of the plurality of current-steering multiplexers;
a plurality of column select signals, wherein each current-steering multiplexer of the plurality of current-steering multiplexers is coupled to a column select signal of the plurality of column select signals; and
a plurality of current sense amplifiers, wherein a bidirectional node of each current-steering multiplexer is coupled to a current sense amplifier.

### Claim 13 (depends on 12)

The RRAM array of claim 12, wherein the bidirectional node of each current-steering multiplexer is coupled to current driver.

### Claim 14

A method of manufacturing a resistive random access memory (RRAM) array that supports a redundant column comprising:
fabricating a plurality of row lines;
fabricating a plurality of column lines perpendicular to the plurality of row lines, wherein the plurality of column lines has n+1 column lines and a cross point is formed at each location where a row line of the plurality of row lines crosses a column line of the plurality of column lines;
fabricating an RRAM cell at each cross point;
coupling n current-steering multiplexers to the plurality of column lines, wherein each current-steering multiplexer is coupled to two column lines of the plurality of column lines, has a select input coupled to a column select signal, and has a bidirectional node coupled to a current sense amplifier;
identifying a failed column line; and
based on the identification of the failed column line,
applying a low column select signal at the select input of each current-steering multiplexer coupled to the column line of the plurality of column lines prior to the failed column line to select each column line of the plurality of column lines to the left of the failed column line, and
applying a high column select signal at the select input of each current-steering multiplexer coupled to the column line of the plurality of column lines after the failed column line to select each column line of the plurality of column lines to the right of the failed column line.

### Claim 15 (depends on 14)

The method of claim 14 wherein identifying a failed column line includes identifying a failed RRAM cell on the failed column line.

### Claim 16 (depends on 1)

The RRAM array of claim 1, wherein the RRAM array is a symmetric array.

### Claim 17 (depends on 1)

The RRAM array of claim 1, wherein the RRAM array is an asymmetric array.

### Claim 18

A resistive random access memory (RRAM) array to support a redundant column comprising:
a plurality of row lines;
a plurality of column lines perpendicular to the plurality of row lines, wherein a cross point is formed at each location where a row line of the plurality of row lines crosses a column line of the plurality of column lines;
an RRAM cell at each cross point;
a plurality of current-steering multiplexers coupled to the plurality of column lines, wherein a first column line of the plurality of column lines is coupled to a first current-steering multiplexer of the plurality of current-steering multiplexers, a last column line of the plurality of column lines is coupled to a last current-steering multiplexer of the plurality of current-steering multiplexers, and each of a remainder of column lines of the plurality of column lines is coupled to two current-steering multiplexers of the plurality of current-steering multiplexers;
a plurality of current sense amplifiers, wherein each current-steering multiplexer has an output coupled to a current sense amplifier of the plurality of current sense amplifiers; and
a plurality of column select signals, wherein each current-steering multiplexer of the plurality of current-steering multiplexers is coupled to a column select signal of the plurality of column select signals.

### Claim 19 (depends on 18)

The RRAM array of claim 18, wherein a second column line of the plurality of column lines has failed and wherein a first column select signal associated with a first current-steering multiplexer of the plurality of current-steering multiplexers and a first column line of the plurality of column lines is set low and a second column select signal associated with a second current-steering multiplexer of the plurality of current-steering multiplexers and the second column line is set high to avoid the failed second column line.

### Claim 20 (depends on 18)

The RRAM array of claim 18, wherein each RRAM cell is bipolar.

### Claim 21 (depends on 18)

The RRAM array of claim 18, wherein each current-steering multiplexer of the plurality of current-steering multiplexers further comprises a first n-channel field-effect transistor (nFET) and a second nFET.

### Claim 22 (depends on 18)

The RRAM array of claim 18, wherein each current-steering multiplexer of the plurality of current-steering multiplexers further comprises a first full pass gate and a second full pass gate.

### Claim 23 (depends on 18)

The RRAM array of claim 18, wherein each RRAM cell is unipolar.

### Claim 24 (depends on 18)

The RRAM array of claim 18, wherein each current-steering multiplexer of the plurality of current-steering multiplexers further comprises a first p-channel field-effect transistor (pFET) and a second pFET.

### Claim 25 (depends on 18)

The RRAM array of claim 18, wherein, when one of the plurality of column lines fails, the RRAM array to avoid the failed column line by applying a low column select signal to each current-steering multiplexer coupled to a column line of the plurality of column lines prior to the failed column line, and applying a high column select signal to each current-steering multiplexer coupled to a column line of the plurality of column lines after the failed column line.

### Claim 26 (depends on 18)

The RRAM array of claim 18, further comprising:
a plurality of switches to support a redundant row, the plurality of switches coupled to the plurality of row lines, wherein a first row line of the plurality of row lines is coupled to a first switch of the plurality of switches, a last row line of the plurality of row lines is coupled to a last switch of the plurality of switches, and each of a remainder of row lines of the plurality of row lines is coupled to two switches of the plurality of switches;
a plurality of row select signals, wherein each switch of the plurality of switches is coupled to a row select signal of the plurality of row select signals; and
a plurality of drivers, wherein each switch is coupled to a driver.