# US 2018/0025789 A1 · Shared error detection and correction memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0025789 A1 - Document ID: US20180025789A1 - Status: Published application - Kind: A1 - Application number: 15/217,719 - Filed: 2016-07-22 - Published: 2018-01-25 - Earliest claimed: 2016-07-22 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Chiaki Dono; Taihei Shido; Yuki Ebihara - Web page: https://patentgrep.com/patent/US20180025789A1 ## CPC - G11C 29/38: Response verification devices - G11C 29/1201: {comprising I/O circuitry} - G11C 29/36: Data generation devices, e.g. data inverters - G11C 29/44: Indication or identification of errors, e.g. for repair - G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths - G11C 29/76: {using address translation or modifications} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups. ## Claims ### Claim 1 An apparatus comprising a first chip, the first chip comprising, on a single semiconductor substrate: a set of first terminals; a plurality of circuit groups, each of the plurality of circuit groups including a set of circuit blocks being configured to electrically couple to the set of first terminals; a control circuit configured to select one of the plurality of circuit groups and electrically couple the set of first terminals to the set of circuit blocks of the one of the plurality of circuit groups; a plurality of terminal groups, each of the plurality of terminal groups including a set of second terminals, each of the plurality of terminal groups being provided correspondingly to each of the plurality of circuit groups, the set of second terminals of each of the plurality of terminal groups being smaller in number than the set of circuit blocks of a corresponding one of the plurality of circuit groups; and a remapping circuit configured to couple the set of second terminals of each of the plurality of terminal groups to selected ones of the set of circuit blocks of the corresponding one of the plurality of circuit groups. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first terminals are smaller in number than the set of circuit blocks of each of the plurality of circuit groups, the control circuit being configured to electrically couple at least one of the set of first terminals in common to at least two of the set of circuit blocks of the selected one of the plurality of circuit groups and electrically couple remaining one or ones of the set of first terminals to remaining one or ones of the set of circuit blocks of the selected one of the plurality of circuit groups. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein each of the set of first terminals is exposed on an outside of the first chip and each of the set of circuit blocks of each of the plurality of circuit groups includes a third terminal exposed on the outside of the first chip. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the first chip further comprises: a substrate; and a plurality of additional terminal groups, each of the plurality of additional terminal groups including a set of through substrate electrodes each penetrating the substrate, the set of through substrate electrodes of each of the plurality of additional terminal groups being coupled to the set of second terminals of a corresponding one of the plurality of terminal groups. ### Claim 5 (depends on 3) The apparatus of claim 3, wherein the third terminal of each of the plurality of circuit blocks of each of the circuit groups is configured to selectively couple to one of a bump or and each of the first terminals. ### Claim 6 (depends on 1) The apparatus of claim 1, further comprising a main substrate on which the first chip is stacked and a controller chip stacked on the main substrate, the controller chip being configured to control each of the plurality of circuit groups. ### Claim 7 An apparatus comprising an interface chip, the interface chip comprising: a direct access test port circuit comprising a set of test ports configured to receive a set of test control signals, the direct access test port circuit being configured to provide a set of groups of first test signals, each group of first test signals in the set of groups of first test signals being based on a corresponding test control signal of the set of test control signals; a control circuit configured to provide the set of groups of first test signals from the set of test ports; a plurality of circuit blocks, each circuit block being configured to receive one group of the set of groups of first test signals from the control circuit, each circuit block being further configured to receive an input signal from an interconnect, and each circuit block being further configured to provide internal signals based on either the one group of first test signals or the input signal; a plurality of TSV terminals coupled to a plurality of conductive vias; and a remapping circuit configured to couple the plurality of circuit blocks to the corresponding plurality of TSV terminals, wherein the plurality of TSV terminals is smaller in number than the plurality of circuit blocks. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein each circuit block is further configured to provide the internal signals based on the one group of first test signals responsive to a test enable signal indicative of a test regarding a write operation. ### Claim 9 (depends on 7) The apparatus of claim 7, wherein the remapping circuit comprises a plurality of multiplexers, each of the plurality of multiplexers is configured to couple to one or more circuit blocks. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein each of the plurality of multiplexers is configured to selectively couple the one of the one or more circuit blocks, responsive to a corresponding lane shift enable signal from the control circuit. ### Claim 11 (depends on 9) The apparatus of claim 9, wherein the plurality of circuit blocks comprises a set of first circuit blocks corresponding to a first byte and a set of second circuit blocks corresponding to a second byte, wherein the plurality of multiplexers comprises: a set of first multiplexers, each first multiplexer being configured to couple to one or more corresponding first circuit blocks of the set of first circuit blocks; and a set of second multiplexers, each second multiplexer being configured to couple to one or more corresponding second circuit blocks of the set of second circuit blocks. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the set of second multiplexers comprises one second multiplexer comprising a first input coupled to one first circuit block of the set of first circuit blocks and a second input coupled to one second circuit block of the set of second circuit blocks, and wherein the one first circuit block of the set of first circuit blocks is a redundancy circuit block which is used when the plurality of circuit blocks comprises an inactive circuit block. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the inactive circuit block becomes inactive responsive to an active fault lane signal from the control circuit. ### Claim 14 (depends on 12) The apparatus of claim 12, wherein the redundancy circuit block is configured to receive at least one lane enable signal, a first group of first test signals corresponding to the first byte and a second group of first test signals corresponding to the second byte from one of the set of second circuit blocks from the control circuit, and further configured to provide the internal signals based on either the first group of first test signals or the second group of first test signals to the one second multiplexer responsive to the at least one lane enable signal. ### Claim 15 (depends on 7) The apparatus of claim 7, wherein the plurality of circuit blocks comprises a set of first circuit blocks corresponding to a first byte and a set of second circuit blocks corresponding to a second byte, wherein the remapping circuit comprises a plurality of multiplexers, each of the plurality of multiplexer is configured to couple to one or more TSV terminals, and wherein the plurality of multiplexers comprises: a set of first multiplexers, each first multiplexer being configured to couple to one or more first TSV terminals among the plurality of TSV terminals to a corresponding first circuit block of the set of first circuit blocks; and a set of second multiplexers, each second multiplexer being configured to couple to one or more second TSV terminals among the plurality of TSV terminals to a corresponding second circuit block of the set of second circuit blocks. ### Claim 16 A method of providing test signals on an interface chip, comprising: receiving a set of test control signals; providing a set of groups of first test signals, each group of first test signals in the set of groups of first test signals being based on a corresponding test control signal of the set of test control signals; receiving one group of first test signals among the set of groups of first test signals and an input signal from an interconnect at one circuit block among a plurality of circuit blocks; providing internal signals from the one circuit block, based on either the one group of first test signals or the input signal; and selectively coupling the one circuit block to a corresponding one TSV terminal of a plurality of TSV terminals coupled to a corresponding conductive via by a remapping circuit responsive to a corresponding lane shift enable signal, wherein the plurality of TSV terminals is smaller in number than the plurality of circuit blocks. ### Claim 17 (depends on 16) The method of claim 16, wherein the remapping circuit comprises a plurality of multiplexers configured to couple to one or more circuit blocks, and wherein selectively coupling the one circuit block to the corresponding one TSV terminal of the plurality of TSV terminals comprises selectively coupling one of the one or more circuit blocks to the corresponding one TSV terminal by each of the plurality of multiplexers, responsive to the corresponding lane shift enable signal. ### Claim 18 (depends on 17) The method of claim 17, wherein the plurality of circuit blocks comprises a set of first circuit blocks corresponding to a first byte and a set of second circuit blocks corresponding to a second byte, and wherein the plurality of multiplexers comprises: a set of first multiplexers, each first multiplexer being configured to couple to one or more corresponding first circuit blocks of the set of first circuit blocks; and a set of second multiplexers, each second multiplexer being configured to couple to one or more corresponding second circuit blocks of the set of second circuit blocks. ### Claim 19 (depends on 18) The method of claim 18, wherein the set of second multiplexers comprises one second multiplexer comprising a first input coupled to one first circuit block of the set of first circuit blocks and a second input coupled to one second circuit block of the set of second circuit blocks, wherein the one first circuit block of the set of first circuit blocks is a redundancy circuit block which is used when the plurality of circuit blocks comprises an inactive circuit block, wherein receiving the one group of first test signals among the set of groups of first test signals and the input signal at the one circuit block among the plurality of circuit blocks comprises: receiving at least one lane enable signal, a first group of first test signals corresponding to the first byte and a second group of first test signals corresponding to the second byte from one of the set of second circuit blocks by the redundancy circuit block, and wherein providing the internal signals from the one circuit block, based on either the one group of first test signals or the input signal comprises: providing the internal signals based on either the first group of first test signals or the second group of first test signals to the one second multiplexer responsive to the at least one lane enable signal. ### Claim 20 (depends on 16) The method of claim 16, wherein the remapping circuit comprises a plurality of multiplexers configured to couple to one or more TSV terminals, and wherein coupling the one circuit block to the corresponding one TSV terminal of the plurality of TSV terminals comprises selectively coupling one of the one or more TSV terminals to the one circuit block by each of the plurality of multiplexers, responsive to a corresponding lane shift enable signal.