# US 2018/0025785 A1 · One-time programmable memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0025785 A1 - Document ID: US20180025785A1 - Status: Published application - Kind: A1 - Application number: 15/619,300 - Filed: 2017-06-09 - Published: 2018-01-25 - Earliest claimed: 2016-07-25 - Assignees: MagnaChip Semiconductor, Ltd. - Applicants: MagnaChip Semiconductor, Ltd. - Inventors: Duk Ju JEONG - Web page: https://patentgrep.com/patent/US20180025785A1 ## CPC - G11C 17/18: Auxiliary circuits, e.g. for writing into memory - G11C 17/16: using electrically-fusible links - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Provided is a one-time programmable (OTP) memory device, which includes a data input circuit that receives a supply voltage and applies the supply voltage to one of a plurality of bit lines that is selected by a write switch, and an OTP memory cell array including a plurality of OTP memory cells arranged in a plurality of rows and columns. The OTP memory cells on the same row connected to the same bit line. The OTP memory device also includes a column decoder that selects one of the plurality of columns of the OTP memory cells to apply the supply voltage thereto, and a detection amplifier that performs a read operation of the OTP memory cells connected to one of the plurality of bit lines that is selected by a read switch. ## Claims ### Claim 1 A one-time programmable (OTP) memory device comprising: a data input circuit that receives a supply voltage and applies the supply voltage to one of a plurality of bit lines that is selected by a write switch; an OTP memory cell array comprising a plurality of OTP memory cells arranged in a plurality of rows and columns, the OTP memory cells on the same row connected to the same bit line; a column decoder that selects one of the plurality of columns of the OTP memory cells to apply the supply voltage thereto; and a detection amplifier that performs a read operation of the OTP memory cells connected to one of the plurality of bit lines that is selected by a read switch. ### Claim 2 (depends on 1) The OTP memory device of claim 1, wherein the OTP memory cells selected simultaneously by the write switch and the column decoder perform a programming operation. ### Claim 3 (depends on 2) The OTP memory device of claim 2, wherein the OTP memory cells selected simultaneously by the write switch and the column decoder receive the supply voltage from each of the data input circuit and the column decoder. ### Claim 4 (depends on 1) The OTP memory device of claim 1, wherein the plurality of OTP memory cells are formed without a source line, and wherein the OTP memory cells selected simultaneously by the write switch and the column decoder perform a programming operation using the supply voltage applied to the bit line. ### Claim 5 (depends on 1) The OTP memory device of claim 1, wherein each of the plurality of OTP memory cells comprises: a switching element that is connected to the bit line and is turned on or off in response to a selection by the column decoder; and an OTP cell that performs, when the switching element is turned on, a programming or read operation using a voltage applied to the bit line. ### Claim 6 (depends on 5) The OTP memory device of claim 5, wherein each of the OTP memory cells selected simultaneously by the write switch and the column decoder turns on the switching element to apply the supply voltage, which is received via a drain of the switching element, directly to the OTP cell. ### Claim 7 (depends on 5) The OTP memory device of claim 5, wherein each of the OTP memory cells selected simultaneously by the read switch and the column decoder turns on the switching element to perform a read operation. ### Claim 8 (depends on 1) The OTP memory device of claim 1, wherein the plurality of OTP memory cells are formed on a single P-well. ### Claim 9 (depends on 1) The OTP memory device of claim 1, further comprising a power selection circuit that receives the supply voltage from an external supply voltage pad and provides the supply voltage to the data input circuit and the column decoder. ### Claim 10 (depends on 9) The OTP memory device of claim 9, wherein the power selection circuit selects the supply voltage or a rated voltage using first and second switching devices and provides the selected voltage to the data input circuit and the column decoder, and wherein the first and second switching devices are opened and closed based on a write enable signal and a write enable bar signal. ### Claim 11 (depends on 10) The OTP memory device of claim 10, wherein the power selection circuit shifts the write enable signal and the write enable bar signal and turns on one of the first and second switching devices to select the supply voltage or the rated voltage. ### Claim 12 (depends on 9) The OTP memory device of claim 9, wherein the OTP memory cells selected simultaneously by the write switch and the column decoder perform a programming operation using the supply voltage provided from the power selection circuit. ### Claim 13 (depends on 1) The OTP memory device of claim 1, further comprising an address decoder that shifts a level of a power voltage prior to converting the power voltage to the supply voltage, and pre-decodes the level-shifted supply voltage. ### Claim 14 (depends on 13) The OTP memory device of claim 13, wherein the column decoder generates a read-and-write enable signal based on the pre-decoded supply voltage, and provides the read-and-write enable signal to the plurality of OTP memory cells. ### Claim 15 (depends on 1) The OTP memory device of claim 1, further comprising a switch control circuit that generates a write switch enable signal that turns on the write switch, and a read switch enable signal that turns on the read switch. ### Claim 16 (depends on 1) The OTP memory device of claim 1, further comprising a plurality of input/output (IO) modules, wherein each IO module comprises the OTP memory cell array, the data input circuit, and the detection amplifier. ### Claim 17 (depends on 16) The OTP memory device of claim 16, wherein the plurality of OTP memory cells included in each IO module are controlled by the same column decoder. ### Claim 18 A one-time programmable (OTP) memory device, comprising: a data input circuit that receives a supply voltage and applies the supply voltage to one of a plurality of bit line that is selected by a write switch; an OTP memory cell array comprising a plurality of OTP memory cells arranged in a plurality of rows and columns, the OTP memory cells arranged on the same row connected to the same bit line; a column decoder that selects one of the plurality of columns of the OTP memory cells to apply the supply voltage thereto; a power selection circuit that receives the supply voltage from a supply voltage pad and provides the supply voltage to the data input circuit and the column decoder; and an address decoder that shifts a level of a power voltage to generate the supply voltage, and pre-decodes the level-shifted supply voltage. ### Claim 19 A one-time programmable (OTP) memory device, comprising: a plurality of OTP memory cells arranged in a plurality of rows and columns; a plurality of bit lines, each bit line connected to the OTP memory cells on the same row; a data input circuit that applies a supply voltage to one of the plurality of bit lines; and a column decoder that applies the supply voltage to one of the plurality of columns of the OTP memory cells, wherein a programming operation is performed on the OTP memory cell that is on the column applied with the supply voltage and connected to the bit line applied with the supply voltage. ### Claim 20 (depends on 19) The OTP memory device of claim 19, further comprising a write switch that selects one of the plurality of bit lines for the programming operation.