# US 2018/0025784 A1 · Memory device and operating method thereof

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- Number: US 2018/0025784 A1
- Document ID: US20180025784A1
- Status: Published application
- Kind: A1
- Application number: 15/466,070
- Filed: 2017-03-22
- Published: 2018-01-25
- Earliest claimed: 2016-07-19
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Hee Youl LEE
- Web page: https://patentgrep.com/patent/US20180025784A1

## CPC

- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 16/32: Timing circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Disclosed are a memory device, including: a memory block including a plurality of cell strings; a peripheral circuit configured to set voltages for a program operation of selected memory cells in the cell strings, and program the selected memory cells by using the set voltages; and a control circuit configured to control the peripheral circuit so that the selected memory cells are programmed in response to a program command, and increase a channel voltage of non-selected cell strings including non-selected memory cells while the selected memory cells are programmed, and an operating method thereof.

## Claims

### Claim 1

A memory device, comprising:
a memory block including a plurality of cell strings;
a peripheral circuit configured to set voltages for a program operation of selected memory cells in the cell strings, and program the selected memory cells by using the set voltages; and
a control circuit configured to control the peripheral circuit for programming the selected memory cells in response to a program command, and to increase a channel voltage of non-selected cell strings including non-selected memory cells while the selected memory cells are programmed.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the control circuit controls the peripheral circuit for increasing the channel voltage according to at least one of a target voltage of the selected memory cells, a verify voltage used in the program operation, and a program time taken for the program operation.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the control circuit controls the peripheral circuit for increasing the channel voltage stepwise according to an increase in the at least one of the target voltage, the verify voltage, and the program time.

### Claim 4 (depends on 2)

The memory device of claim 2, wherein when the channel voltage is increased according to the target voltage, the control circuit compares a pre-set target voltage with a target voltage, which is set to be higher than the pre-set target voltage, and maintains the channel voltage with a precharge voltage when the target voltage is lower than the pre-set target voltage, and increases the precharge voltage when the target voltage is equal to or higher than the pre-set target voltage.

### Claim 5 (depends on 2)

The memory device of claim 2, wherein when the channel voltage is increased according to the verify voltage, the control circuit compares a pre-set verify voltage with a verify voltage, which is set to be higher than the pre-set verify voltage, and maintains the channel voltage with a precharge voltage when the verify voltage is lower than the pre-set verify voltage, increases the precharge voltage when the verify voltage is equal to or higher than the pre-set verify voltage.

### Claim 6 (depends on 2)

The memory device of claim 2, wherein when the channel voltage is increased according to the program time, the control circuit compares a pre-set program time with a program time, which is set to be longer than the pre-set program time, and maintains the channel voltage with a precharge voltage when the program time is shorter than the pre-set program time, and increases the precharge voltage when the program time is equal to or longer than the pre-set program time.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the cell strings include source select transistors, memory cells, and drain select transistors connected between a source line and bit lines.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein when the channel voltage is increased through a voltage applied to the source line, the peripheral circuit increases a source line voltage applied to the source line.

### Claim 9 (depends on 7)

The memory device of claim 7, wherein when the channel voltage is increased through a voltage applied to the source line, the peripheral circuit increases a source select line voltage for turning on the source select transistors.

### Claim 10 (depends on 7)

The memory device of claim 7, wherein when the channel voltage is increased through a voltage applied to the bit lines, the peripheral circuit increases a drain select line voltage for turning on the drain select transistors.

### Claim 11

An operating method of a memory device, comprising:
comparing a pre-set program operation condition with a program operation condition;
maintaining a channel voltage of non-selected cell strings with a set-up level when the program operation condition is lower than the pre-set program operation condition as a result of the comparison;
increasing the channel voltage when the program operation condition is equal to or higher than the pre-set program operation condition; and
programming selected memory cells included in selected cell strings based on one of the maintained channel voltage and the increased channel voltage.

### Claim 12 (depends on 11)

The operating method of claim 11, wherein the program operation condition includes at least one of a target voltage, a verify voltage, and a program time.

### Claim 13 (depends on 12)

The operating method of claim 12, wherein the target voltage is a voltage for completing a program operation of the selected memory cells,
the verify voltage is a voltage for verifying the selected memory cells; and
the program time is a time for which the program operation of the selected memory cells is performed.

### Claim 14 (depends on 11)

The operating method of claim 11, wherein the channel voltage is increased through a source line voltage applied to a source line, which is commonly connected to the selected cell strings and the non-selected cell strings, or is increased by a precharge voltage applied to bit lines connected to the selected cell strings and the non-selected cell strings.

### Claim 15 (depends on 14)

The operating method of claim 14, further comprising:
when the channel voltage is increased through the source line, increasing a turn-on voltage of source select transistors for transferring a voltage applied to the source line to the selected cell strings and the non-selected cell strings.

### Claim 16 (depends on 14)

The operating method of claim 14, further comprising:
when the channel voltage is increased through the bit lines, increasing a turn-on voltage of drain select transistors for transferring a voltage applied to the bit lines to the selected cell strings and the non-selected cell strings.

### Claim 17

An operating method of a memory device, comprising:
increasing a voltage applied to channels of non-selected cell strings during a program operation according to an increase of at least one of a target voltage, a verify voltage, and the program time of the program operation; and
programming selected memory cells based on the increased voltage.

### Claim 18 (depends on 17)

The operating method of claim 17, wherein when at least one of the target voltage, the verify voltage, and the program time is lower or shorter than a pre-set target voltage, a pre-set verify voltage, and a pre-set program time, respectively, a voltage applied to the channel is maintained, and
when at least one of the target voltage, the verify voltage, and the program time is equal to or higher or longer than the pre-set target voltage, the pre-set verify voltage, and the pre-set program time, respectively, a voltage applied to the channel is further increased than before.

### Claim 19 (depends on 18)

The operating method of claim 18, wherein each of the pre-set target voltage, the pre-set verify voltage, and the pre-set program time includes a plurality of values.