# US 2018/0025783 A1 · Non-volatile memory device and method of fabricating the same

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- Number: US 2018/0025783 A1
- Document ID: US20180025783A1
- Status: Published application
- Kind: A1
- Application number: 15/658,293
- Filed: 2017-07-24
- Published: 2018-01-25
- Earliest claimed: 2016-07-25
- Assignees: SK hynix Inc.; Sogang University Research Foundation
- Applicants: SK hynix Inc.; Sogang University Research Foundation
- Inventors: Woo Young CHOI
- Web page: https://patentgrep.com/patent/US20180025783A1

## CPC

- G11C 16/34: Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 2216/02: Structural aspects of erasable programmable read-only memories
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory includes a channel layer; a data storage layer disposed on the channel layer; a plurality of control gates arranged on the data storage layer and spaced apart from one another; and one or more sub-gates, at least one of the sub-gates being arranged between two adjacent control gates.

## Claims

### Claim 1

A non-volatile memory device, comprising:
a channel layer;
a data storage layer disposed on the channel layer;
a plurality of control gates arranged on the data storage layer and spaced apart from one another; and
one or more sub-gates, at least one of the sub-gates being arranged between two adjacent control gates.

### Claim 2 (depends on 1)

The non-volatile memory device of claim 1, wherein, during a programming operation, a voltage is applied to a sub-gate adjacent to a selected control gate from among the plurality of control gates, the voltage applied to the adjacent sub-gate having a polarity opposite to a polarity of a program voltage, the program voltage being applied to the selected control gate.

### Claim 3 (depends on 1)

The non-volatile memory device of claim 1, wherein, during a programming operation, an unselected sub-gate is electrically floated or an inhibit voltage is applied to the unselected sub-gate.

### Claim 4 (depends on 1)

The non-volatile memory device of claim 1, wherein, a ratio of a width of each sub-gate to a distance from a sub-gate to an adjacent control gate is from 0.1 to 1.

### Claim 5 (depends on 1)

The non-volatile memory device of claim 1, wherein the one or more sub-gates comprise a conductive material identical to a conductive material of the plurality of control gates.

### Claim 6 (depends on 1)

The non-volatile memory device of claim 1, wherein each of the sub-gates comprises any one of a doped poly-silicon, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), nickel (Ni), chromium (Cr), manganese (Mn), palladium (Pd), zirconium (Zr), gold (Au), platinum (Pt), iridium (Ir), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), vanadium (V), erbium (Er), a conductive silicide thereof, a conductive nitride thereof, and a conductive oxide thereof.

### Claim 7 (depends on 1)

The non-volatile memory device of claim 1, wherein the data storage layer comprises:
a tunnelling insulation layer contacting the channel layer;
a blocking insulation layer contacting the plurality of control gates; and
a charge trapping storage layer disposed between the tunnelling insulation layer and the blocking insulation layer.

### Claim 8 (depends on 1)

The non-volatile memory device of claim 1, wherein the channel layer extends in a direction vertical to a main surface of a substrate on which the non-volatile memory device is to be formed.

### Claim 9 (depends on 1)

The non-volatile memory device of claim 1, wherein the data storage layer is shared by the plurality of control gates.

### Claim 10 (depends on 9)

The non-volatile memory device of claim 9, wherein the non-volatile memory device has a SMArT structure, a bit cost scalable (BiCS) structure, a piped BiCS (P-BiCS) structure, a vertical-recess-array-transistor) structure, or a terabit cell array transistor (TCAT) structure.

### Claim 11

A non-volatile memory device, comprising:
memory cell strings, each memory cell string comprising a plurality of memory cells connected to one another in series;
wordlines connected to control gates of the plurality of memory cells, respectively;
sub-wordlines, at least one of the sub-wordlines being arranged between two adjacent wordlines;
bitlines connected to first ends of the memory cell strings, respectively;
a row decoder electrically connected to the plurality of memory cells via the wordlines and the sub-wordlines; and
a column decoder electrically connected to the memory cell strings via the bitlines.

### Claim 12 (depends on 11)

The non-volatile memory device of claim 11, wherein a number of the sub-wordlines is one less than a total number of the wordlines.

### Claim 13 (depends on 11)

The non-volatile memory device of claim 11, wherein, during a programming operation, a voltage having a polarity opposite to a polarity of a program voltage is applied to a sub-wordline adjacent to a selected wordline from among the plurality of wordline, the program voltage being applied to the selected wordline.

### Claim 14 (depends on 11)

The non-volatile memory device of claim 11, wherein, during a programming operation, an unselected sub-wordline is electrically floated or an inhibit voltage is applied to the unselected sub-wordline.

### Claim 15

A method of fabricating a non-volatile memory device, the method comprising:
forming a stacked structure by alternately and repeatedly forming one or more insulation layers and a plurality of conductive layers on a substrate, wherein the plurality of conductive layers comprise first conductive layers for forming control gates and second conductive layers for forming sub-gates, at least one of the sub-gates being formed between two adjacent control gates;
forming via holes extending in a vertical direction that is normal to a main surface of the substrate by patterning the stacked structure;
forming a data storage layer on a sidewall of each of the via holes; and
forming a semiconductor pillar comprising a channel layer in a groove region defined by the data storage layer in each of the via holes.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first conductive layers and the second conductive layers comprise an identical conductive material.

### Claim 17 (depends on 15)

The method of claim 15, wherein the second conductive layer comprises any one of a doped poly-silicon, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), nickel (Ni), chromium (Cr), manganese (Mn), palladium (Pd), zirconium (Zr), gold (Au), platinum (Pt), iridium (Ir), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), vanadium (V), erbium (Er), a conductive silicide thereof, a conductive nitride thereof, and a conductive oxide thereof.

### Claim 18 (depends on 15)

The method of claim 15, wherein, a ratio of a width of the second conductive layer to a distance from the second conductive layer to an adjacent first conductive layer is from 0.1 to 1.

### Claim 19 (depends on 15)

The method of claim 15, wherein forming the data storage layer comprises:
forming a blocking insulation layer on the sidewall of each of the via holes so that the blocking insulation layer contacts the control gates formed by patterning the stacked structure;
forming a charge trapping storage layer on the blocking insulation layer; and
forming a tunnelling insulation layer on the charge trapping storage layer,
wherein the tunneling insulation layer contacts the channel layer.