# US 2018/0025779 A1 · Nonvolatile Nanotube Switches and Systems Using Same

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- Number: US 2018/0025779 A1
- Document ID: US20180025779A1
- Status: Published application
- Kind: A1
- Application number: 15/707,724
- Filed: 2017-09-18
- Published: 2018-01-25
- Earliest claimed: 2005-05-09
- Assignees: Nantero, Inc.
- Applicants: Nantero, Inc.
- Inventors: Claude L. Bertin; Eliodor G. Ghenciu; Thomas Rueckes; H. Montgomery Manning
- Web page: https://patentgrep.com/patent/US20180025779A1

## CPC

- G11C 13/0097: {Erasing, e.g. resetting, circuits or methods}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/003: {Cell access}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 13/025: {using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes}
- H10B 63/00: Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 62/123: {comprising junctions}
- H10D 62/813: {Quantum wire structures}
- H10D 62/882: {Graphene}
- H10K 85/221: {Carbon nanotubes}
- G11C 2013/009: {Write using potential difference applied between cell electrodes}
- G11C 2213/19: Memory cell comprising at least a nanowire and only two terminals
- G11C 2213/35: Material including carbon, e.g. graphite, grapheme
- G11C 2213/71: Three dimensional array
- G11C 2213/72: Array wherein the access device being a diode
- G11C 2213/75: Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
- G11C 2213/79: Array wherein the access device being a transistor
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.

## Claims

### Claim 1

A non-volatile nanotube switch, comprising:
a pair of conductive terminals;
a nonwoven fabric article having a plurality of nanotubes forming an electrical network, the plurality of nanotubes having a plurality of defects selected to provide pre-determined electrical characteristics of the network, the article electrically interposed between the pair of conductive terminals;
control circuitry in electrical communication with the pair of conductive terminals, the control circuitry applying electrical stimulus to at least a portion of the nonwoven fabric article through the pair of conductive terminals;
wherein the nonwoven fabric article is switchable among a plurality of electronic states in response to the electrical stimulus, the electronic states corresponding to the resistances of the nonwoven fabric article.

### Claim 2 (depends on 1)

The switch of claim 1 wherein the nanotubes comprise a selected composition of single walled nanotubes and multi-walled nanotubes.

### Claim 3 (depends on 2)

The switch of claim 2 wherein the proportion of single walled nanotubes to multi-walled nanotubes is selected to increase the quantity of defects comprising the plurality of defects.

### Claim 4 (depends on 1)

The switch of claim 1 wherein the plurality of defects is formed from chemical treatments comprising at least one of sulfuric acid and nitric acid.

### Claim 5 (depends on 1)

The switch of claim 1 wherein the plurality of defects is formed from ion implantation treatments.

### Claim 6 (depends on 5)

The switch of claim 5 wherein the ion implantation provides ions that partially permeate the nonwoven fabric article.

### Claim 7 (depends on 1)

The switch of claim 1 wherein the plurality of electrical stimuli from the control circuitry comprises a voltage of less than approximately 5 volts.

### Claim 8 (depends on 1)

The switch of claim 1 wherein the plurality of electrical stimuli from the control circuitry comprises a SET current of approximately 1-3 μA and a RESET current of approximately 10-50 /μA.