# US 2018/0025775 A1 · Memory cell having a magnetic josephson junction device with a doped magnetic layer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0025775 A1 - Document ID: US20180025775A1 - Status: Published application - Kind: A1 - Application number: 15/218,031 - Filed: 2016-07-24 - Published: 2018-01-25 - Earliest claimed: 2016-07-24 - Assignees: Microsoft Technology Licensing, LLC - Applicants: Microsoft Technology Licensing, LLC - Inventors: Thomas F. Ambrose - Web page: https://patentgrep.com/patent/US20180025775A1 ## CPC - G11C 11/44: using super-conductive elements, e.g. cryotron - G11C 11/1673: {Reading or sensing circuits or methods} - G11C 11/1675: {Writing or programming circuits or methods} - H10N 50/85: Materials of the active region - H10N 60/12: Josephson-effect devices - H10N 60/30: Devices switchable between superconducting and normal states - H10N 60/805: {for Josephson-effect devices} - H10N 60/85: Superconducting active materials - G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell} - H10N 50/10: Magnetoresistive devices - G11C: STATIC STORES (semiconductor memory devices H10B) - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract Examples described in this disclosure relate to a memory cell having a magnetic Josephson junction device with a doped magnetic layer. In one example, a memory cell including a magnetic Josephson junction (MJJ) device is provided. The MJJ device may include at least a first layer formed above a second layer and a third layer formed below the second layer, where the first layer is a free magnetic layer, the second layer is a non-magnetic layer, where the third layer is a fixed magnetic layer. The free magnetic layer may comprise a magnetic alloy doped with at least one of Vanadium, Zirconium, Molybdenum, or Hafnium, and the fixed magnetic layer may comprise an un-doped second magnetic alloy. ## Claims ### Claim 1 A memory cell, wherein the memory cell is configured to be either in a voltage state or a zero state, the memory cell comprising: a read bit-line; a read word-line; a first magnetic Josephson junction (MJJ) device connected to the read bit-line via a first inductor, the first MJJ device comprising at least a first layer formed above a second layer and a third layer formed below the second layer, wherein the first layer is a free magnetic layer, the second layer is a non-magnetic layer, wherein the third layer is a fixed magnetic layer, wherein the free magnetic layer comprises a magnetic alloy doped with at least one of Vanadium, Zirconium, Molybdenum, or Hafnium, and wherein the fixed magnetic layer comprises an un-doped second magnetic alloy; and a second magnetic Josephson junction (MJJ) device connected to the read bit-line via a second inductor, the second MJJ device comprising at least a fourth layer formed above a fifth layer and a sixth layer formed below the fifth layer, wherein the fourth layer is a free magnetic layer, the fifth layer is a non-magnetic layer, wherein the sixth layer is a fixed magnetic layer, wherein the free magnetic layer comprises a magnetic alloy doped with at least one of Vanadium, Zirconium, Molybdenum, or Hafnium, and wherein the fixed magnetic layer comprises an un-doped second magnetic alloy, wherein during a read operation, the read word-line is configured to apply a word read current to the memory cell and the read bit-line is configured to apply a bit read current to the first MJJ device via the first inductor and to the second MJJ device via the second inductor to change a state of the memory cell from the zero state to the voltage state. ### Claim 2 (depends on 1) The memory cell of claim 1, wherein the magnetic alloy comprises at least one of a nickel-iron alloy, a nickel-cobalt alloy, an iron-cobalt alloy, or a cobalt-nickel-iron alloy. ### Claim 3 (depends on 1) The memory cell of claim 1, wherein the free magnetic layer comprises the magnetic alloy doped with only Vanadium. ### Claim 4 (depends on 3) The memory cell of claim 3, wherein a concentration of the Vanadium is in a range between 5 atomic percent to 40 atomic percent of the magnetic alloy doped with only Vanadium. ### Claim 5 (depends on 1) The memory cell of claim 1, wherein the free magnetic layer comprises the magnetic alloy doped with only Zirconium. ### Claim 6 (depends on 5) The memory cell of claim 5, wherein a concentration of the Zirconium is in a range between 2 atomic percent to 20 atomic percent of the magnetic alloy doped with only Zirconium. ### Claim 7 (depends on 1) The memory cell of claim 1, wherein the non-magnetic layer comprises at least one of Vanadium, Molybdenum, Copper, Aluminum, Tantalum, or Chromium. ### Claim 8 (depends on 1) The memory cell of claim 1, wherein the memory cell is configured to be in a first magnetization state or a second magnetization state, and wherein the first magnetization state corresponds to a first configuration of magnetization of the free magnetic layer and the second magnetization state corresponds to a second configuration of magnetization of the free magnetic layer, wherein the first configuration of the magnetization of the free magnetic layer corresponds to a first magnetic field that is parallel to a magnetic field of the fixed magnetic layer and the second configuration of the magnetization of the free magnetic layer corresponds to a second magnetic field that is anti-parallel to the magnetic field of the fixed magnetic layer. ### Claim 9 (depends on 1) The memory cell of claim 1 further comprising a fourth layer formed above the first layer and a fifth layer formed below the third layer, wherein each of the fourth layer and the fifth layer comprises Niobium. ### Claim 10 A memory cell, wherein the memory cell is configured to be either in a voltage state or a zero state, the memory cell comprising: a read bit-line; a read word-line; a magnetic Josephson junction (MJJ) device connected to the read bit-line via a first inductor, the first MJJ device comprising at least a first layer formed above a second layer and a third layer formed below the second layer, wherein the first layer is a free magnetic layer, the second layer is a non-magnetic layer, and the third layer is a fixed magnetic layer, wherein the free magnetic layer comprises a nickel-iron alloy doped with only Vanadium, wherein a concentration of the Vanadium is in a range between 5 atomic percent to 20 atomic percent, wherein the fixed magnetic layer comprises a nickel-iron alloy doped with only Vanadium, and wherein a concentration of the Vanadium is in a range between 5 atomic percent to 10 atomic percent; and a second magnetic Josephson junction (MJJ) device connected to the read bit-line via a second inductor, the second MJJ device comprising at least a fourth layer formed above a fifth layer and a sixth layer formed below the fifth layer, wherein the fourth layer is a free magnetic layer, the fifth layer is a non-magnetic layer, wherein the sixth layer is a fixed magnetic layer, wherein the free magnetic layer comprises a nickel-iron alloy doped with only Vanadium, wherein a concentration of the Vanadium is in a range between 5 atomic percent to 20 atomic percent, wherein the fixed magnetic layer comprises a nickel-iron alloy doped with only Vanadium, and wherein a concentration of the Vanadium is in a range between 5 atomic percent to 10 atomic percent, wherein during a read operation, the read word-line is configured to apply a word read current to the memory cell and the read bit-line is configured to apply a bit read current to the first MJJ device via the first inductor and to the second MJJ device via the second inductor to change a state of the memory cell from the zero state to the voltage state. ### Claim 11 (depends on 10) The memory cell of claim 10, wherein the non-magnetic layer comprises at least one of Vanadium, Molybdenum, Copper, Aluminum, Tantalum, or Chromium. ### Claim 12 (depends on 10) The memory cell of claim 10, wherein the memory cell is configured to be in a first magnetization state or a second magnetization state, and wherein the first magnetization state corresponds to a first configuration of magnetization of the free magnetic layer and the second magnetization state corresponds to a second configuration of magnetization of the free magnetic layer, wherein the first configuration of the magnetization of the free magnetic layer corresponds to a first magnetic field that is parallel to a magnetic field of the fixed magnetic layer and the second configuration of the magnetization of the free magnetic layer corresponds to a second magnetic field that is anti-parallel to the magnetic field of the fixed magnetic layer. ### Claim 13 (depends on 10) The memory cell of claim 10, wherein the free magnetic layer has a thickness between 10 Angstroms to 25 Angstroms. ### Claim 14 (depends on 13) The memory cell of claim 13, wherein the fixed magnetic layer has a thickness between 10 Angstroms to 25 Angstroms. ### Claim at position 15 -20. (canceled) ### Claim 21 (depends on 1) The memory cell of claim 1, wherein, during the read operation, the read bit-line is configured to receive current from a bit-line driver in response to at least one control signal received via an address bus, wherein the at least one control signal comprises at least one single-flux-quantum (SFQ) pulse. ### Claim 22 (depends on 1) The memory cell of claim 1, wherein, during the read operation, the read word-line is configured to receive current from a word-line driver in response to at least one control signal received via an address bus, wherein the at least one control signal comprises at least one single-flux-quantum (SFQ) pulse. ### Claim 23 (depends on 10) The memory cell of claim 10, wherein, during the read operation, the read bit-line is configured to receive current from a bit-line driver in response to at least one control signal received via an address bus, wherein the at least one control signal comprises at least one single-flux-quantum (SFQ) pulse. ### Claim 24 (depends on 10) The memory cell of claim 10, wherein, during the read operation, the read word-line is configured to receive current from a word-line driver in response to at least one control signal received via an address bus, wherein the at least one control signal comprises at least one single-flux-quantum (SFQ) pulse.