# US 2018/0025774 A1 · Memory Cell of Static Random Access Memory Based on Resistance Hardening

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- Number: US 2018/0025774 A1
- Document ID: US20180025774A1
- Status: Published application
- Kind: A1
- Application number: 15/550,898
- Filed: 2015-03-27
- Published: 2018-01-25
- Earliest claimed: 2015-03-27
- Assignees: Institute of Automation, Chinese Academy of Sciences
- Applicants: Institute of Automation Chinese Academy of Sciences
- Inventors: Jingqiu Wang; Li Liu; Liang Chen
- Web page: https://patentgrep.com/patent/US20180025774A1

## CPC

- G11C 11/417: for memory cells of the field-effect type
- G11C 11/412: using field-effect transistors only
- G11C 11/4125: {Cells incorporating circuit means for protecting against loss of information}
- G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present invention provides a memory cell of a static random access memory based on resistance reinforcement, which includes a latch circuit and a bit selection circuit. The latch circuit consists of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, a first resistance-capacitance network and a second resistance-capacitance network. The bit selection circuit consists of NMOS transistors N5 and N6. The latch circuit form four storage nodes X1, X1B, X2, X2B. Compared to the conventional memory cell of a 6T structure, a resistance-capacitance network is added, so that without changing the original read operation circuit and without obviously increasing complexity, the memory cell is prevented from having single event upset at a cost of increasing a small amount of area, thus ensuring correctness of data.

## Claims

### Claim 1

A memory cell of static random access memory based on resistance reinforcement comprising a latch circuit and a bit selection circuit, characterized in that the latch circuit consists of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, a first resistance-capacitance network and a second resistance-capacitance network; the bit selection circuit consists of NMOS transistors N5 and N6; the latch circuit forms four storage nodes X1, X1B, X2, X2B;
wherein a drain of P1 is connected to X1, a source thereof is connected to a power supply, and a gate thereof is connected to X1B; an input terminal and an output terminal of the first resistance-capacitance network are connected to X1 and X2 respectively; a drain of N1 is connected to X2, a source thereof is connected to the ground, and a gate thereof is connected to X2B;
wherein a drain of P2 is connected to X1B, a source thereof is connected to a power supply, and a gate thereof is connected to X1; an input terminal and an output terminal of the second resistance-capacitance network are connected to X1B and X2B respectively; a drain of N2 is connected to X2B, a source thereof is connected to the ground, and a gate thereof is connected to X2;
wherein a drain of N5 is connected to X2 or X1, a drain of N6 is accordingly connected to X2B or X1B; a source of N5 is connected to a bit line BL; a source of N6 is connected to a complementary bit line BLB; gates of N5 and N6 are connected to each other and are connected to a word line WL.

### Claim 2 (depends on 1)

The memory cell of static random access memory based on resistance reinforcement according to claim 1, characterized in that the first resistance-capacitance network consists of R1 and C1, and the second resistance-capacitance network consists of R2 and C2;
wherein two terminals of R1 are connected to X1 and X2 respectively; one terminal of C1 is connected to X1 and the other terminal thereof is connected to the ground;
wherein two terminals of R2 are connected to X1B and X2B respectively; one terminal of C2 is connected to X1B and the other terminal thereof is connected to the ground.

### Claim 3 (depends on 1)

The memory cell of static random access memory based on resistance reinforcement according to claim 1, characterized in that the first resistance-capacitance network consists of a PMOS transistor P3 and an NMOS transistor N3 that are always on so as to act as resistance-capacitance isolation nodes, and the second resistance-capacitance network consists of a PMOS transistor P4 and an NMOS transistor N4 that are always on so as to act as resistance-capacitance isolation nodes;
wherein a storage node X3 is formed between P3 and N3; and a storage node X3B is formed between P4 and N4;
wherein a source of P3 is connected to X1, a drain thereof is connected to X3, a gate thereof is connected to the ground, and its substrate is connected to a power supply, so that it is always on; a drain of N3 is connected to X3, a source thereof is connected to X2, a gate thereof is connected to a power supply and a substrate thereof is connected to the ground, so that it is always on;
wherein a source of P4 is connected to X1B, a drain thereof is connected to X3B, a gate thereof is connected to the ground, and its substrate is connected to a power supply, so that it is always on; a drain of N3 is connected to X3B, a source thereof is connected to X2B, a gate thereof is connected to a power supply and a substrate thereof is connected to the ground, so that it is always on.