# US 2018/0025773 A1 · Precharging and refreshing banks in memory device with bank group architecture

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- Number: US 2018/0025773 A1
- Document ID: US20180025773A1
- Status: Published application
- Kind: A1
- Application number: 15/639,725
- Filed: 2017-06-30
- Published: 2018-01-25
- Earliest claimed: 2015-02-28
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Kuljit S. BAINS; John B. HALBERT; Nadav BONEN; Tomer LEVY
- Web page: https://patentgrep.com/patent/US20180025773A1

## CPC

- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G11C 11/40603: {Arbitration, priority and concurrent access to memory cells for read/write or refresh operations}
- G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh}
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.

## Claims

### Claim at position 1

1-26. (canceled)

### Claim 27

A dynamic random access memory (DRAM) device comprising:
multiple banks of memory addressable by bank group identifier and by bank identifier;
interface hardware to couple to multiple signal lines of a command and address bus; and
logic to identify a signal pattern at the interface hardware as a same bank command including a bank identifier and not including a bank group identifier, the logic to apply the same bank command to banks identified by the bank identifier across multiple different bank groups.

### Claim 28 (depends on 27)

The DRAM device of claim 27, wherein the same bank command comprises a same bank refresh command.

### Claim 29 (depends on 28)

The DRAM device of claim 28, wherein the logic includes both an internal bank counter to track a refresh count to specific banks, and a global refresh counter.

### Claim 30 (depends on 27)

The DRAM device of claim 27, wherein the same bank command comprises a same bank precharge command.

### Claim 31 (depends on 27)

The DRAM device of claim 27, wherein the same bank command comprises a sequence of a same bank precharge command and a same bank refresh command to access the same bank identifier in different bank groups.

### Claim 32 (depends on 27)

The DRAM device of claim 27, wherein the signal pattern includes a single signal line logic value to differentiate the same bank command from a command directed to bank and bank group.

### Claim 33 (depends on 27)

The DRAM device of claim 27, wherein the multiple bank groups includes 2 or 4 bank groups.

### Claim 34 (depends on 33)

The DRAM device of claim 33, wherein the multiple banks includes 8 banks in each bank group.

### Claim 35 (depends on 27)

The DRAM device of claim 27, wherein the DRAM device comprises a memory device compatible with a double date rate (DDR) standard.

### Claim 36 (depends on 35)

The DRAM device of claim 35, wherein the DRAM device comprises a memory device compatible with a DDR version 5 (DDR5) standard.

### Claim 37

A system comprising:
a memory controller to manage refresh of associated memory devices; and
multiple memory devices coupled to the memory controller, wherein a memory device includes
multiple banks of memory addressable by bank group identifier and by bank identifier;
interface hardware to couple to multiple signal lines of a command and address bus; and
logic to identify a signal pattern at the interface hardware as a same bank command including a bank identifier and not including a bank group identifier, the logic to apply the same bank command to banks identified by the bank identifier across multiple different bank groups.

### Claim 38 (depends on 37)

The system of claim 37, wherein the same bank command comprises a same bank refresh command.

### Claim 39 (depends on 38)

The system of claim 38, wherein the logic includes both an internal bank counter to track a refresh count to specific banks, and a global refresh counter.

### Claim 40 (depends on 37)

The system of claim 37, wherein the same bank command comprises a same bank precharge command.

### Claim 41 (depends on 37)

The system of claim 37, wherein the same bank command comprises a sequence of a same bank precharge command and a same bank refresh command to access the same bank identifier in different bank groups.

### Claim 42 (depends on 37)

The system of claim 37, wherein the signal pattern includes a single signal line logic value to differentiate the same bank command from a command directed to bank and bank group.

### Claim 43 (depends on 37)

The system of claim 37, wherein the multiple bank groups includes 2 or 4 bank groups.

### Claim 44 (depends on 43)

The system of claim 43, wherein the multiple banks includes 8 banks in each bank group.

### Claim 45 (depends on 37)

The system of claim 37, wherein the DRAM device comprises a memory device compatible with a double date rate version 5 (DDR5) standard.

### Claim 46 (depends on 37)

The system of claim 37, further comprising one or more of:
at least one processor communicatively coupled to the memory controller;
a display communicatively coupled to at least one processor; or
a network interface communicatively coupled to at least one processor.