# US 2018/0025772 A1 · Semiconductor devices having a refresh operation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0025772 A1 - Document ID: US20180025772A1 - Status: Published application - Kind: A1 - Application number: 15/427,572 - Filed: 2017-02-08 - Published: 2018-01-25 - Earliest claimed: 2016-07-25 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Dong Uk LEE; Dae Suk KIM - Web page: https://patentgrep.com/patent/US20180025772A1 ## CPC - G11C 11/40618: {Refresh operations over multiple banks or interleaving} - G11C 8/10: Decoders - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/408: Address circuits - G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge} - G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G11C 8/06: Address interface arrangements, e.g. address buffers - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor device includes a first row address generation circuit and a second row address generation circuit. The first row address generation circuit generates a first row address for refreshing memory cells connected to word lines included in a first up block and a second up block from a refresh command and an active signal in response to a period selection signal and a first period signal. The second row address generation circuit generates a second row address for refreshing memory cells connected to word lines included in a first down block and a second down block from the refresh command and the active signal in response to the period selection signal and a second period signal. ## Claims ### Claim 1 A semiconductor device comprising: a first row address generation circuit configured to generate a first row address for refreshing memory cells connected to first group word lines included in a first up block and a second up block from a refresh command and an active signal in response to a period selection signal and a first period signal; a second row address generation circuit configured to generate a second row address for refreshing memory cells connected to second group word lines included in a first down block and a second down block from the refresh command and the active signal in response to the period selection signal and a second period signal; and a period signal generation circuit configured to generate the first period signal, the second period signal and the period selection signal in response to a first start signal, a first end signal, a second start signal and a second end signal. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the first up block and the first down block are included in a first bank; and wherein the second up block and the second down block are included in a second bank. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the period selection signal has a first logic level to generate the first row address from the refresh command; and wherein the period selection signal has a second logic level to generate the second row address from the refresh command. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the first period signal is enabled during a period from a point of time that the first row address for activating a first word line included in the first group word lines is generated till a point of time that the first row address for activating an Nth word line included in the first group word lines is generated. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the first row address generation circuit is configured to generate the first row address from the active signal during a period that the first period signal is enabled. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the second row address generation circuit is configured to generate the second row address from the active signal during a period that the second period signal is enabled. ### Claim 7 (depends on 1) The semiconductor device of claim 1, further comprising an address selection circuit configured to output the first row address or the second row address as a refresh address. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the first row address generation circuit is configured to generate the first start signal which is enabled if the first row address for activating a first word line included in the first group word lines is generated; and wherein the first row address generation circuit is configured to generate the first end signal which is enabled if the first row address for activating an Nth word line included in the first group word lines is generated. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the second row address generation circuit is configured to generate a second start signal which is enabled if the second row address for activating a first word line included in the second group word lines is generated; and wherein the second row address generation circuit is configured to generate a second end signal which is enabled if the second row address for activating an Nth word line included in the second group word lines is generated. ### Claim 10 (canceled) ### Claim 11 (depends on 1) The semiconductor device of claim 1, wherein the first period signal is enabled during a period from a point of time that the first start signal is enabled till a point of time that the first end signal is enabled; wherein the second period signal is enabled during a period from a point of time that the second start signal is enabled till a point of time that the second end signal is enabled; and wherein the period selection signal is enabled during a period from a point of time that the first start signal is enabled till a point of time that the second start signal is enabled. ### Claim 12 (depends on 1) The semiconductor device of claim 1, further comprising an address transmission circuit configured to output the first row address and the second row address as a first transmission address and a second transmission address in response to the first start signal and the second start signal. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the first and second transmission addresses are used to apply the refresh command to the first and second row address generation circuits. ### Claim 14 (depends on 1) The semiconductor device of claim 1, wherein the first row address generation circuit includes: a command control signal generation circuit configured to generate a command control signal from the refresh command in response to the period selection signal; an active control signal generation circuit configured to generate an active control signal from the active signal in response to the first period signal; a count control signal generation circuit configured to generate a count control signal for counting the first row address in response to the command control signal and the active control signal. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein the command control signal generation circuit includes: a pull-down signal generation circuit configured to buffer the refresh command to generate a pull-down signal in response to the period selection signal; and a command control signal driving circuit configured to drive the command control signal in response to a reset signal and the pull-down signal. ### Claim 16 (depends on 14) The semiconductor device of claim 14, wherein the active control signal generation circuit is configured to block input of the active signal if the active control signal is enabled. ### Claim 17 (depends on 14) The semiconductor device of claim 14, wherein the active control signal generation circuit includes: a pulse generation circuit configured to generate a pulse which is created if both of the first period signal and the active signal are enabled; a pull-down pulse generation circuit configured to generate a pull-down pulse in response to the pulse; and an active control signal driving circuit configured to drive the active control signal in response to a reset signal and the pull-down pulse. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein generation of the pull-down pulse terminates if the active control signal is enabled. ### Claim 19 (depends on 14) The semiconductor device of claim 14, wherein the first row address generation circuit further includes a counter configured to output the first row address that is counted in response to the count control signal. ### Claim 20 (depends on 14) The semiconductor device of claim 14, wherein the first row address generation circuit further includes an address sensing circuit configured to sense the first row address to generate the first start signal which is enabled to activate a first word line included in the first and second up blocks and to generate the first end signal which is enabled to activate an Nth word line included in the first and second up blocks. ### Claim 21 A semiconductor device comprising: a row address generation circuit configured to generate a row address for refreshing memory cells connected to group word lines included in a first block and a second block from a refresh command and an active signal in response to a period selection signal and a period signal; and a period signal generation circuit configured to generate the period signal and the period selection signal in response to a start signal and an end signal. ### Claim 22 (depends on 21) The semiconductor device of claim 21, wherein the row address generation circuit includes: a command control signal generation circuit configured to generate a command control signal from the refresh command in response to the period selection signal; an active control signal generation circuit configured to generate an active control signal from the active signal in response to the period signal; a count control signal generation circuit configured to generate a count control signal for counting the row address in response to the command control signal and the active control signal. ### Claim 23 (depends on 21) The semiconductor device of claim 21, wherein the row address has a logic level combination for activating the group word lines included in the first block and the second block; and wherein the first block is included in the first bank and the second block is included in the second bank. ### Claim 24 (depends on 22) The semiconductor device of claim 22, wherein the command control signal generation circuit includes: a pull-down signal generation circuit configured to buffer the refresh command to generate a pull-down signal in response to the period selection signal; and a command control signal driving circuit configured to drive the command control signal in response to a reset signal and the pull-down signal. ### Claim 25 (depends on 22) The semiconductor device of claim 22, wherein the active control signal generation circuit is configured to block input of the active signal if the active control signal is enabled. ### Claim 26 (depends on 22) The semiconductor device of claim 22, wherein the active control signal generation circuit includes: a pulse generation circuit configured to generate a pulse which is created if both of the period signal and the active signal are enabled; a pull-down pulse generation circuit configured to generate a pull-down pulse in response to the pulse; and an active control signal driving circuit configured to drive the active control signal in response to a reset signal and the pull-down pulse. ### Claim 27 (depends on 26) The semiconductor device of claim 26, wherein generation of the pull-down pulse terminates if the active control signal is enabled. ### Claim 28 (depends on 22) The semiconductor device of claim 22, wherein the row address generation circuit further includes a counter configured to output the row address that is counted in response to the count control signal. ### Claim 29 (depends on 22) The semiconductor device of claim 22, wherein the row address generation circuit further includes an address sensing circuit configured to sense the row address to generate the start signal which is enabled to activate a first word line included in the group word lines and to generate the end signal which is enabled to activate an Nth word line included in the group word lines.