# US 2018/0025771 A1 · Directed per bank refresh command

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- Number: US 2018/0025771 A1
- Document ID: US20180025771A1
- Status: Published application
- Kind: A1
- Application number: 15/611,455
- Filed: 2017-06-01
- Published: 2018-01-25
- Earliest claimed: 2013-09-27
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Kuljit S. BAINS
- Web page: https://patentgrep.com/patent/US20180025771A1

## CPC

- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 11/406: Management or control of the refreshing or charge-regeneration cycles
- G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh}
- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device includes a per bank refresh counter applicable to multiple banks in a group. The memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a per bank refresh in response to receiving the per bank refresh command. The memory device refreshes a row identified by a row address counter for a bank identified by the per bank refresh command. The memory device increments the per bank refresh counter in response to receiving the per bank refresh command, and increments the row address counter when the per bank refresh counter is reset, either by rolling over or by a reset condition.

## Claims

### Claim 1

A method comprising:
receiving a per bank refresh command at a memory device from a memory controller;
performing a per bank refresh in response to receiving the per bank refresh command for a bank identified by the command at a row identified by a row address counter;
incrementing a per bank refresh counter in response to receiving the per bank refresh command;
determining if incrementing the per bank refresh counter causes the per bank refresh counter to roll over; and
when the per bank refresh counter rolls over, incrementing the row address counter;
otherwise, maintaining the row address counter at a current value for a subsequent per bank refresh command.

### Claim 2 (depends on 1)

The method of claim 1, wherein receiving the per bank refresh command comprises receiving a command to refresh a bank out of bank address order.

### Claim 3 (depends on 2)

The method of claim 2, wherein receiving the command out of bank address order comprises receiving the command to refresh the banks in a random order.

### Claim 4 (depends on 1)

The method of claim 1, wherein performing the per bank refresh comprises refreshing all banks via per bank refresh command prior to repeating a per bank refresh of any of the banks.

### Claim 5 (depends on 1)

The method of claim 1, wherein incrementing the per bank refresh counter comprises incrementing a counter applicable to all banks in a channel.

### Claim 6 (depends on 1)

The method of claim 1, wherein incrementing the per bank refresh counter comprises incrementing a counter applicable to multiple banks, for a subset of banks in a channel.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
clearing the per bank refresh counter in response to detecting a reset condition.

### Claim 8 (depends on 7)

The method of claim 7, wherein the reset condition comprises a memory subsystem reset signal generated in response to a power-up condition.

### Claim 9 (depends on 7)

The method of claim 7, wherein the reset condition comprises exit of the memory device from self-refresh.

### Claim 10 (depends on 7)

The method of claim 7, wherein the reset condition comprises receiving an all bank refresh command from the memory controller.

### Claim 11

A memory device comprising:
multiple banks of memory, each having multiple rows;
connectors to couple to a memory controller and receive a per bank refresh command from the memory controller, the per bank refresh command identifying a specific one of the multiple bank to refresh;
a row address counter to indicate a row address to refresh for the specific bank identified by the per bank refresh command;
a per bank refresh counter to increment in response to receiving the per bank refresh command; and
logic to determine if incrementing the per bank refresh counter causes the per bank refresh counter to roll over, and when the per bank refresh counter rolls over, to increment the row address counter; otherwise, to maintain the row address counter at a current value for a subsequent per bank refresh command.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein the banks of memory are grouped as separate subsets, and wherein the per bank refresh counter is applicable to all banks in a subset, but not to banks of other subsets.

### Claim 13 (depends on 11)

The memory device of claim 11, the logic to further clear the per bank refresh counter in response to detecting a reset condition.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the reset condition comprises one of a memory subsystem reset signal generated in response to a power-up condition, exit of the memory device from self-refresh, or receiving an all bank refresh command from the memory controller.

### Claim 15

A memory subsystem comprising:
connectors to couple to a memory device having multiple rows of memory;
a memory controller device coupled to the connectors, the memory controller to
determine to issue a per bank refresh to refresh a specific one of multiple memory banks instead of an all bank refresh;
determine a per bank ordering pattern for the multiple memory banks;
transmit a per bank refresh command to the memory device to cause the memory device to perform a per bank refresh for a bank identified by the refresh command at a row identified by a row address counter, wherein the memory device increments a per bank refresh counter in response to the refresh command, and increments a row address counter only in response to a per bank refresh counter reset condition, and otherwise, maintains the row address counter at a current value for a subsequent per bank refresh command.

### Claim 16 (depends on 15)

The memory subsystem of claim 15, wherein the order pattern comprises an order out of bank address order.

### Claim 17 (depends on 16)

The memory subsystem of claim 16, wherein the out of bank address order pattern comprises a different order for each cycle of per bank refresh commands.

### Claim 18 (depends on 15)

The memory subsystem of claim 15, wherein the memory controller to determine to issue the per bank refresh further comprises the memory controller to refresh all banks via per bank refresh command prior to repeating a per bank refresh of any of the banks.

### Claim 19 (depends on 15)

The memory subsystem of claim 15, wherein the reset condition comprises one of a rolling over of the per bank refresh counter, a memory subsystem reset signal generated in response to a power-up condition, exit of the memory device from self-refresh, or receiving an all bank refresh command from the memory controller.