# US 2018/0025758 A1 · Apparatuses and methods for storing a data value in a sensing circuitry element

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- Number: US 2018/0025758 A1
- Document ID: US20180025758A1
- Status: Published application
- Kind: A1
- Application number: 15/693,064
- Filed: 2017-08-31
- Published: 2018-01-25
- Earliest claimed: 2016-07-21
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Daniel B. Penney; Harish N. Venkata; Guy S. Perry
- Web page: https://patentgrep.com/patent/US20180025758A1

## CPC

- G11C 7/065: {Differential amplifiers of latching type}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 8/10: Decoders
- G11C 11/403: with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4094: Bit-line management or control circuits
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A method, comprising:
moving a first data value from a first storage location of a compute component of a sensing circuitry element to a second storage location of the compute component,
wherein moving the second data value includes applying a charge sharing operation between the first storage location and the second storage location.

### Claim 22 (depends on 21)

The method of claim 21, further comprising controlling logic circuity of the sensing circuitry element to perform a logical operation on the first data value and the second data value.

### Claim 23 (depends on 21)

The method of claim 21, wherein the charge sharing operation comprises shorting a node of the first storage location to a node of the second storage location.

### Claim 24 (depends on 21)

The method of claim 21, wherein the charge sharing operation comprises gating nodes associated with the logic circuitry to isolate logic circuitry during the charge sharing operation.

### Claim 25 (depends on 21)

The method of claim 21, wherein the charge sharing operation comprises:
applying a voltage to the first storage location;
applying a voltage to the second storage location; and
stopping the application of the voltage to the first storage location in response to the voltage being applied to the second storage location.

### Claim 26 (depends on 21)

The method of claim 21, further comprising storing, in the first storage location, a third data value resulting from a logical operation performed using the first data value and the second data value.

### Claim 27 (depends on 21)

The method of claim 21, wherein applying the charge sharing operation comprises stopping an application of a voltage to the first storage location and the second storage location to share a charge associated with the first storage location and the second storage location.

### Claim 28

An apparatus, comprising:
a sensing circuitry element including a sense amplifier and a compute component, the compute component comprising a first storage location and a second storage location; and
a controller coupled to the sensing circuitry element and configured to:
move a first data value from the first storage location of the compute component to the second storage location of the compute component by applying a charge sharing operation between the first storage location and the second storage location.

### Claim 29 (depends on 28)

The apparatus of claim 28, wherein the controller is further configured to cause a node of the first storage location to be shorted to a node of the second storage location as part of the charge sharing operation.

### Claim 30 (depends on 28)

The apparatus of claim 28, wherein:
the sensing circuitry element further comprises logic, and
the controller is configured to cause the logic circuitry to perform a logical operation on the first data value and the second data value.

### Claim 31 (depends on 30)

The apparatus of claim 30, wherein the controller is further configured to cause a third data value resulting from performance of the logical operation to be stored in the first storage location.

### Claim 32 (depends on 28)

The apparatus of claim 28, further comprising a plurality of transistors coupled to the compute component, wherein the controller is configured to assert a precharge signal to gates transistors among the plurality of transistors as party of application of the charge sharing operation.

### Claim 33

An apparatus, comprising:
a sensing circuitry element, including:
a sense amplifier coupled to logic circuitry;
a first storage location coupled to the logic circuitry; and
a second storage location coupled to the first storage location; and
a controller coupled to the sensing circuitry element, wherein the controller is configured to:
disable, during a clock cycle, a power associated with the first storage location; and
disable, during the clock cycle, a power associated with the second storage location such that a charge between the first storage location and the second storage location is shared.

### Claim 34 (depends on 33)

The apparatus of claim 33, wherein the controller is further configured to cause a logical operation to be performed on a first data value stored in the sense amplifier and a second data value stored in the second storage location.

### Claim 35 (depends on 34)

The apparatus of claim 34, wherein the controller is further configured to cause a result of the logical operation to be stored in the first storage location.

### Claim 36 (depends on 34)

The apparatus of claim 34, wherein the controller is configured to cause the logical operation to be performed without transferring the first data value or the second data value via an input/output (I/O) line.

### Claim 37 (depends on 33)

The apparatus of claim 33, wherein the sensing circuitry element is configured to act as a single-bit processing element capable of performing a logical operation in parallel with other sensing circuitry elements.

### Claim 38 (depends on 33)

The apparatus of claim 33, further comprising:
a first transistor coupled to the first storage location;
a second transistor coupled to the second storage location, wherein a gate of the first transistor and a gate of the second transistor are coupled to a precharge signal line.

### Claim 39 (depends on 33)

The apparatus of claim 33, wherein the controller is configured to control coupling a node of the first storage location to a node of the second location such that the node of the first storage location is shorted to the node of the second location such that the charge between the first storage location and the second storage location is shared.

### Claim 40 (depends on 33)

The apparatus of claim 33, wherein the controller is configured to cause a data value stored in the first storage location to be shifted to the second storage location.