# US 2018/0025695 A1 · Gate Driver on Array Circuit and Driving Method Thereof, and Display Device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0025695 A1 - Document ID: US20180025695A1 - Status: Published application - Kind: A1 - Application number: 15/656,419 - Filed: 2017-07-21 - Published: 2018-01-25 - Earliest claimed: 2016-07-22 - Assignees: Boe Technology Group Co., Ltd. - Applicants: Boe Technology Group Co., Ltd. - Inventors: Mingfu HAN; Guangliang SHANG; Seungwoo HAN; Zhihe JIN; Xing YAO; Haoliang ZHENG; Lijun YUAN; Zhichong WANG - Web page: https://patentgrep.com/patent/US20180025695A1 ## CPC - G09G 3/3677: {suitable for active matrices only} - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2330/08: Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract The present invention discloses a gate driver on array circuit and a driving method thereof, and a display device. The gate driver on array circuit comprises a first gate driver on array sub-circuit and a second gate driver on array sub-circuit; the first gate driver on array sub-circuit is configured to drive in a first working state which is a state in which no defect occurs in the first gate driver on array sub-circuit; the second gate driver on array sub-circuit is configured to drive in a second working state which is a state in which a defect occurs in the first gate driver on array sub-circuit. The present invention improves the yield rate of the gate driver on array circuit. ## Claims ### Claim 1 A gate driver on array circuit, comprising a first gate driver on array sub-circuit and a second gate driver on array sub-circuit; the first gate driver on array sub-circuit is configured to drive gate lines in a first working state, wherein the first working state is a state in which no defect occurs in the first gate driver on array sub-circuit; the second gate driver on array sub-circuit is configured to drive the gate lines in a second working state, wherein the second working state is a state in which a defect occurs in the first gate driver on array sub-circuit. ### Claim 2 (depends on 1) The gate driver on array circuit of claim 1, wherein the first gate driver on array sub-circuit is configured to perform driving when no defect occurs therein and to stop driving when a defect occurs therein; the second gate driver on array sub-circuit is configured to perform driving when the first gate driver on array sub-circuit stops driving due to occurrence of a defect in the first gate driver on array sub-circuit. ### Claim 3 (depends on 1) The gate driver on array circuit of claim 1, wherein the first gate driver on array sub-circuit and the second gate driver on array sub-circuit each include a plurality of cascaded shift registers, and output signal terminals of the shift registers in the first gate driver on array sub-circuit are connected to those of respective shift registers in the second gate driver on array sub-circuit. ### Claim 4 (depends on 3) The gate driver on array circuit of claim 3, wherein the first gate driver on array sub-circuit is configured to, in the first working state, cause high level signals to be applied to clock signal terminals of the shift registers in the first gate driver on array sub-circuit and low level signals to be applied to other terminals of the shift registers in the first gate driver on array sub-circuit; or the first gate driver on array sub-circuit is configured to, in the first working state, cause clock signals to be applied to the clock signal terminals of the shift registers in the first gate driver on array sub-circuit and low level signals to be applied to other terminals of the shift registers in the first gate driver on array sub-circuit. ### Claim 5 (depends on 3) The gate driver on array circuit of claim 3, wherein each of the shift registers includes a first transistor; a control electrode of the first transistor is connected to an input signal terminal, a first electrode of the first transistor is connected to a first power supply, and a second electrode of the first transistor is connected to a pull-up node. ### Claim 6 (depends on 2) The gate driver on array circuit of claim 2, further comprising a detection circuit and a switching circuit; the detection circuit is configured to detect the first gate driver on array sub-circuit and, when a defect occurs in the first gate driver on array sub-circuit, generate an abnormal signal, generate a starting signal according to the abnormal signal and output the starting signal to the switching circuit; the switching circuit is configured to be started according to the starting signal, and output a switching signal to the first gate driver on array sub-circuit and output the switching signal to the second gate driver on array sub-circuit; the first gate driver on array sub-circuit is configured to stop driving according to the switching signal; the second gate driver on array sub-circuit is configured to drive according to the switching signal. ### Claim 7 (depends on 6) The gate driver on array circuit of claim 6, wherein the first gate driver on array sub-circuit and the second gate driver on array sub-circuit each include a plurality of cascaded shift registers, output signal terminals of the shift registers in the first gate driver on array sub-circuit are connected to those of respective shift registers in the second gate driver on array sub-circuit, and the output signal terminal of a last row of shift register in the first gate driver on array sub-circuit is connected to an input signal terminal of the detection circuit; the switching circuit comprises a plurality of cascaded shift registers, an input signal terminal of a first row of shift register of the switching circuit is connected to an output signal terminal of the detection circuit, an output signal terminal of a last row of shift register of the switching circuit is connected to an input signal terminal of a first row of shift register in the second gate driver on array sub-circuit, and the output signal terminal of the last row of shift register of the switching circuit is connected to a switching signal terminal of the first row of shift register in the first gate driver on array sub-circuit. ### Claim 8 (depends on 7) The gate driver on array circuit of claim 7, wherein the number of rows of the shift registers in the switching circuit is determined according to a blanking time between two frames of display images such that a timing of the switching signal output by the last row of shift register of the switching circuit is the same as that of a frame-start signal of the first row of shift register of the second gate driver on array sub-circuit. ### Claim 9 (depends on 7) The gate driver on array circuit of claim 7, wherein the first row of shift register of the first gate driver on array sub-circuit comprises a switching transistor, a control electrode of the switching transistor is connected to the output signal terminal of the last row of shift register in the switching circuit, a first electrode of the switching transistor is connected to a pull-up node, and a second electrode of the switching transistor is connected to a low level signal terminal. ### Claim 10 (depends on 7) The gate driver on array circuit of claim 7, wherein the detection circuit is an inverter, the abnormal signal is a low level signal, and the starting signal is a high level signal. ### Claim 11 (depends on 1) A display device, comprising the gate driver on array circuit according to claim 1. ### Claim 12 A driving method for a gate driver on array circuit which comprises a first gate driver on array sub-circuit and a second gate driver on array sub-circuit; the method comprises: driving gate lines in a first working state by the first gate driver on array sub-circuit, wherein the first working state is a state in which no defect occurs in the first gate driver on array sub-circuit; and driving the gate lines in a second working state by the second gate driver on array sub-circuit, wherein the second working state is a state in which a defect occurs in the first gate driver on array sub-circuit. ### Claim 13 (depends on 12) The driving method for the gate driver on array circuit of claim 12, wherein the first gate driver on array sub-circuit performs driving when no defect occurs therein and stops driving when a defect occurs therein; the second gate driver on array sub-circuit performs driving when the first gate driver on array sub-circuit stops driving due to occurrence of a defect in the first gate driver on array sub-circuit. ### Claim 14 (depends on 13) The driving method for the gate driver on array circuit of claim 13, wherein the gate driver on array circuit further comprises a detection circuit and a switching circuit; before the second gate driver on array sub-circuit performs driving when the first gate driver on array sub-circuit stops driving due to occurrence of a defect in the first gate driver on array sub-circuit, the method further comprises: detecting, by the detection circuit, the first gate driver on array sub-circuit and generating an abnormal signal when a defect occurs in the first gate driver on array sub-circuit, generating a starting signal according to the abnormal signal and outputting the starting signal to the switching circuit; the switching circuit starting according to the starting signal, outputting a switching signal to the first gate driver on array sub-circuit and outputting the switching signal to the second gate driver on array sub-circuit; and the first gate driver on array sub-circuit stopping driving according to the switching signal; and wherein, the step that the second gate driver on array sub-circuit performs driving when the first gate driver on array sub-circuit stops driving due to occurrence of a defect comprises: the second gate driver on array sub-circuit performing driving according to the switching signal.