# US 2018/0025687 A1 · Display driving circuit, its control method and display device

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- Number: US 2018/0025687 A1
- Document ID: US20180025687A1
- Status: Published application
- Kind: A1
- Application number: 15/652,474
- Filed: 2017-07-18
- Published: 2018-01-25
- Earliest claimed: 2016-07-19
- Assignees: Boe Technology Group Co., Ltd.; Beijing Boe Display Technology Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.; Beijing Boe Display Technology Co., Ltd.
- Inventors: Zheng WANG
- Web page: https://patentgrep.com/patent/US20180025687A1

## CPC

- G09G 3/3677: {suitable for active matrices only}
- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/3696: {Generation of voltages supplied to electrode drivers}
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2330/08: Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The display driving circuit according to an embodiment of the present disclosure includes a characteristic collector, a comparator, a timing controller and a gate driver. The gate driver includes shift register units each including a first pull-down circuit and a second pull-down circuit, and is provided with a first pull-up voltage terminal and a second pull-up voltage terminal; the characteristic collector is configured for collecting a voltage of the first pull-up voltage terminal or the second pull-up voltage terminal, and for outputting a characteristic voltage; the comparator is configured for comparing the characteristic voltage with a reference voltage of a reference voltage terminal; when the comparison result indicates that the characteristic voltage is greater than or equal to the reference voltage, the timing controller generates a timing control signal such that the first pull-up voltage terminal and the second pull-up voltage terminal are caused to output a DC voltage under the control of the timing control signal.

## Claims

### Claim 1

A display driving circuit, comprising a characteristic collector, a comparator, a timing controller and a gate driver;
wherein the gate driver comprises at least two cascade shift register units, the shift register unit comprising a first pull-down circuit connected to a first pull-down node and a second pull-down circuit connected to a second pull-down node; and the gate driver is provided with a first pull-up voltage terminal for charging the first pull-down node and a second pull-up voltage terminal for charging the second pull-down node;
wherein the characteristic collector is connected to a pull-down voltage terminal and a first input terminal of the comparator, and also to the first pull-up voltage terminal or the second pull-up voltage terminal; the characteristic collector is configured for collecting a voltage of the first pull-up voltage terminal or the second pull-up voltage terminal, and for outputting, to the first input terminal of the comparator, a characteristic voltage which conforms to characteristics of the voltage of the first pull-down circuit or the second pull-down circuit;
wherein a second input terminal of the comparator is connected to a reference voltage terminal and an output terminal of the comparator is connected to the timing controller; and the comparator is configured for comparing the characteristic voltage with a reference voltage of the reference voltage terminal; and
wherein the timing controller is further connected to the gate driver; and the timing controller is configured for receiving a comparison result from the comparator, and when the comparison result indicates that the characteristic voltage is greater than or equal to the reference voltage, the timing controller generates a timing control signal such that the first pull-up voltage terminal and the second pull-up voltage terminal are caused to output a DC voltage under the control of the timing control signal, thereby causing the first pull-down node and the second pull-down node to be simultaneously charged, and both the first pull-down circuit and the second pull-down circuit to be in a working state.

### Claim 2 (depends on 1)

The display driving circuit according to claim 1, wherein the characteristic collector comprises a first collection transistor and a second collection transistor;
a second electrode of the first collection transistor is connected to a first electrode of the second collection transistor; the first electrode of the second collection transistor is connected to the pull-down voltage terminal; and a second electrode of the second collection transistor is connected to the first input terminal of the comparator; and
a gate electrode and a first electrode of the first collection transistor are connected to the first pull-up voltage terminal, and a gate electrode of the second collection transistor is connected to the first pull-up voltage terminal; or the gate electrode and the first electrode of the first collection transistor are connected to the second pull-up voltage terminal, and the gate electrode of the second collection transistor is connected to the second pull-up voltage terminal.

### Claim 3 (depends on 1)

The display driving circuit according to claim 1, wherein the shift register unit further comprises a pull-up control circuit, a pull-up circuit, a reset circuit, a first pull-down control circuit and a second pull-down control circuit;
the pull-up control circuit is connected to a signal input terminal and a pull-up node, and configured for outputting a voltage of the signal input terminal to the pull-up node under the control of the signal input terminal;
the pull-up circuit is connected to a first clock signal input terminal, the pull-up node and a signal output terminal, and configured for outputting a signal of the first clock signal input terminal to the signal output terminal under the control of the pull-up node;
the reset circuit is connected to a reset signal terminal, the pull-down voltage terminal, the pull-up node and the signal output terminal, and configured for respectively pulling down a potential of the pull-up node and of the signal output terminal to a potential of the pull-down voltage terminal under the control of the reset signal terminal;
the first pull-down control circuit is connected to the first pull-up voltage terminal, a second clock signal input terminal, the reset signal terminal, the pull-up node, the first pull-down node and the pull-down voltage terminal, and configured for outputting a voltage of the first pull-up voltage terminal to the first pull-down node under the control of the second clock signal input terminal and the reset signal terminal, or for pulling down a potential of the first pull-down node to the potential of the pull-down voltage terminal under the control of the pull-up node;
the second pull-down control circuit is connected to the second pull-up voltage terminal, the second clock signal input terminal, the reset signal terminal, the pull-up node, the second pull-down node and the pull-down voltage terminal, and configured for outputting a voltage of the second pull-up voltage terminal to the second pull-down node under the control of the second clock signal input terminal and the reset signal terminal, or for pulling down a potential of the second pull-down node to the potential of the pull-down voltage terminal under the control of the pull-up node;
the first pull-down circuit is further connected to the pull-up node, the signal output terminal and the pull-down voltage terminal, and configured for respectively pulling down a potential of the pull-up node and of the signal output terminal to the potential of the pull-down voltage terminal under the control of the first pull-down node; and
the second pull-down circuit is further connected to the pull-up node, the signal output terminal and the pull-down voltage terminal, and configured for respectively pulling down the potential of the pull-up node and of the signal output terminal to the potential of the pull-down voltage terminal under the control of the second pull-down node.

### Claim 4 (depends on 3)

The display driving circuit according to claim 3, wherein the pull-up control circuit includes a first transistor, and a gate electrode and a first electrode of the first transistor are connected to the signal input terminal, and a second electrode of the first transistor is connected to the pull-up node.

### Claim 5 (depends on 3)

The display driving circuit according to claim 3, wherein the pull-up circuit includes a second transistor and a first capacitor;
a gate electrode of the second transistor is connected to the pull-up node, a first electrode of the second transistor is connected to the first clock signal input terminal and a second electrode of the second transistor is connected to the signal output terminal; and
a first end of the first capacitor is connected to the pull-up node and a second end of the first capacitor is connected to the signal output terminal.

### Claim 6 (depends on 3)

The display driving circuit according to claim 3, wherein the reset circuit includes a third transistor and a fourth transistor;
a gate electrode of the third transistor is connected to the reset signal terminal, a first electrode of the third transistor is connected to the pull-down voltage terminal, and a second electrode of the third transistor is connected to the pull-up node; and
a gate electrode of the fourth transistor is connected to the reset signal terminal, a first electrode of the fourth transistor is connected to the pull-down voltage terminal, and a second electrode of the fourth transistor is connected to the signal output terminal.

### Claim 7 (depends on 3)

The display driving circuit according to claim 3, wherein the first pull-down control circuit includes a fifth transistor, a sixth transistor, and a seventh transistor;
a gate electrode of the fifth transistor is connected to the second clock signal input terminal, a first electrode of the fifth transistor is connected to the first pull-up voltage terminal and a second electrode of the fifth transistor is connected to the first pull-down node;
a gate electrode of the sixth transistor is connected to the reset signal terminal, a first electrode of the sixth transistor is connected to the first pull-up voltage terminal and a second electrode of the sixth transistor is connected to the first pull-down node; and
a gate electrode of the seventh transistor is connected to the pull-up node, a first electrode of the seventh transistor is connected to the pull-down voltage terminal, and the second electrode of the seventh transistor is connected to the first pull-down node.

### Claim 8 (depends on 3)

The display driving circuit according to claim 3, wherein the second pull-down control circuit includes an eighth transistor, a ninth transistor, and a tenth transistor;
a gate electrode of the eighth transistor is connected to the reset signal terminal, a first electrode of the eighth transistor is connected to the second pull-up voltage terminal and a second electrode of the eighth transistor is connected to the second pull-down node;
a gate electrode of the ninth transistor is connected to the second clock signal input terminal, a first electrode of the ninth transistor is connected to the second pull-up voltage terminal and a second electrode of the ninth transistor is connected to the second pull-down node; and
a gate electrode of the tenth transistor is connected to the pull-up node, a first electrode of the tenth transistor is connected to the pull-down voltage terminal, and a second electrode of the tenth transistor is connected to the second pull-down node.

### Claim 9 (depends on 3)

The display driving circuit according to claim 3, wherein the first pull-down circuit includes an eleventh transistor and a twelfth transistor;
a gate electrode of the eleventh transistor is connected to the first pull-down node, a first electrode of the eleventh transistor is connected to the pull-down voltage terminal, and a second electrode of the eleventh transistor is connected to the pull-up node; and
a gate electrode of the twelfth transistor is connected to the first pull-down node, a first electrode of the twelfth transistor is connected to the pull-down voltage terminal, and a second electrode of the twelfth transistor is connected to the signal output terminal.

### Claim 10 (depends on 3)

The display driving circuit according to claim 3, wherein the second pull-down circuit includes a thirteenth transistor and a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to the second pull-down node, a first electrode of the thirteenth transistor is connected to the pull-down voltage terminal, and a second electrode of the thirteenth transistor is connected to the pull-up node; and
a gate electrode of the fourteenth transistor is connected to the second pull-down node, a first electrode of the fourteenth transistor is connected to the pull-down voltage terminal, and a second electrode of the fourteenth transistor is connected to the signal output terminal.

### Claim 11

A method for controlling a display driving circuit, wherein the display driving circuit comprises a characteristic collector, a comparator, a timing controller and a gate driver;
wherein the gate driver comprises at least two cascade shift register units, the shift register unit comprising a first pull-down circuit connected to a first pull-down node and a second pull-down circuit connected to a second pull-down node; and the gate driver is provided with a first pull-up voltage terminal for charging the first pull-down node and a second pull-up voltage terminal for charging the second pull-down node;
wherein the characteristic collector is connected to a pull-down voltage terminal and a first input terminal of the comparator, and also to the first pull-up voltage terminal or the second pull-up voltage terminal; the characteristic collector is configured for collecting a voltage of the first pull-up voltage terminal or the second pull-up voltage terminal, and for outputting, to the first input terminal of the comparator, a characteristic voltage which conforms to characteristics of the voltage of the first pull-down circuit or the second pull-down circuit;
wherein a second input terminal of the comparator is connected to a reference voltage terminal, and an output terminal of the comparator is connected to the timing controller; and the comparator is configured for comparing the characteristic voltage with a reference voltage of the reference voltage terminal; and
wherein the timing controller is further connected to the gate driver; and the timing controller is configured for receiving a comparison result from the comparator, and when the comparison result indicates that the characteristic voltage is greater than or equal to the reference voltage, the timing controller generates a timing control signal such that the first pull-up voltage terminal and the second pull-up voltage terminal are caused to output a DC voltage under the control of the timing control signal, thereby causing the first pull-down node and the second pull-down node to be simultaneously charged, and both the first pull-down circuit and the second pull-down circuit to be in a working state,
the method comprising:
collecting a voltage of the first pull-up voltage terminal or the second pull-up voltage terminal and outputting a characteristic voltage that conforms to characteristics of the voltage of the first pull-down circuit or the second pull-down circuit;
comparing the characteristic voltage with a reference voltage of the reference voltage terminal;
generating a timing control signal when the characteristic voltage is greater than or equal to the reference voltage; and
causing the first pull-up voltage terminal or the second pull-up voltage terminal to output a DC voltage under the control of the timing control signal, thereby causing the first pull-down node and the second pull-down node to be simultaneously charged, and both the first pull-down circuit and the second pull-down circuit to be in a working state.

### Claim 12

A display device, comprising a display driving circuit that comprises a characteristic collector, a comparator, a timing controller and a gate driver;
wherein the gate driver comprises at least two cascade shift register units, the shift register unit comprising a first pull-down circuit connected to a first pull-down node and a second pull-down circuit connected to a second pull-down node; and the gate driver is provided with a first pull-up voltage terminal for charging the first pull-down node and a second pull-up voltage terminal for charging the second pull-down node;
wherein the characteristic collector is connected to a pull-down voltage terminal and a first input terminal of the comparator, and also to the first pull-up voltage terminal or the second pull-up voltage terminal; the characteristic collector is configured for collecting a voltage of the first pull-up voltage terminal or the second pull-up voltage terminal, and for outputting, to the first input terminal of the comparator, a characteristic voltage which conforms to characteristics of the voltage of the first pull-down circuit or the second pull-down circuit;
wherein a second input terminal of the comparator is connected to a reference voltage terminal, and an output terminal of the comparator is connected to the timing controller; and the comparator is configured for comparing the characteristic voltage with a reference voltage of the reference voltage terminal; and
wherein the timing controller is further connected to the gate driver; and the timing controller is configured for receiving a comparison result from the comparator, and when the comparison result indicates that the characteristic voltage is greater than or equal to the reference voltage, the timing controller generates a timing control signal such that the first pull-up voltage terminal and the second pull-up voltage terminal are caused to output a DC voltage under the control of the timing control signal, thereby causing the first pull-down node and the second pull-down node to be simultaneously charged, and both the first pull-down circuit and the second pull-down circuit to be in a working state.

### Claim 13 (depends on 12)

The display device according to claim 12, wherein the characteristic collector comprises a first collection transistor and a second collection transistor;
a second electrode of the first collection transistor is connected to a first electrode of the second collection transistor; the first electrode of the second collection transistor is connected to the pull-down voltage terminal; and a second electrode of the second collection transistor is connected to the first input terminal of the comparator; and
a gate electrode and a first electrode of the first collection transistor are connected to the first pull-up voltage terminal, and a gate electrode of the second collection transistor is connected to the first pull-up voltage terminal; or the gate electrode and the first electrode of the first collection transistor are connected to the second pull-up voltage terminal, and the gate electrode of the second collection transistor is connected to the second pull-up voltage terminal.

### Claim 14 (depends on 12)

The display device according to claim 12, wherein the shift register unit further comprises a pull-up control circuit, a pull-up circuit, a reset circuit, a first pull-down control circuit and a second pull-down control circuit;
the pull-up control circuit is connected to a signal input terminal and a pull-up node, and configured for outputting a voltage of the signal input terminal to the pull-up node under the control of the signal input terminal;
the pull-up circuit is connected to a first clock signal input terminal, the pull-up node and a signal output terminal, and configured for outputting a signal of the first clock signal input terminal to the signal output terminal under the control of the pull-up node;
the reset circuit is connected to a reset signal terminal, the pull-down voltage terminal, the pull-up node and the signal output terminal, and configured for respectively pulling down a potential of the pull-up node and of the signal output terminal to a potential of the pull-down voltage terminal under the control of the reset signal terminal;
the first pull-down control circuit is connected to the first pull-up voltage terminal, a second clock signal input terminal, the reset signal terminal, the pull-up node, the first pull-down node and the pull-down voltage terminal, and configured for outputting a voltage of the first pull-up voltage terminal to the first pull-down node under the control of the second clock signal input terminal and the reset signal terminal, or for pulling down a potential of the first pull-down node to the potential of the pull-down voltage terminal under the control of the pull-up node;
the second pull-down control circuit is connected to the second pull-up voltage terminal, the second clock signal input terminal, the reset signal terminal, the pull-up node, the second pull-down node and the pull-down voltage terminal, and configured for outputting a voltage of the second pull-up voltage terminal to the second pull-down node under the control of the second clock signal input terminal and the reset signal terminal, or for pulling down a potential of the second pull-down node to the potential of the pull-down voltage terminal under the control of the pull-up node;
the first pull-down circuit is further connected to the pull-up node, the signal output terminal and the pull-down voltage terminal, and configured for respectively pulling down a potential of the pull-up node and of the signal output terminal to the potential of the pull-down voltage terminal under the control of the first pull-down node; and
the second pull-down circuit is further connected to the pull-up node, the signal output terminal and the pull-down voltage terminal, and configured for respectively pulling down the potential of the pull-up node and of the signal output terminal to the potential of the pull-down voltage terminal under the control of the second pull-down node.

### Claim 15 (depends on 14)

The display device according to claim 14, wherein the pull-up control circuit includes a first transistor, and a gate electrode and a first electrode of the first transistor are connected to the signal input terminal, and a second electrode of the first transistor is connected to the pull-up node.

### Claim 16 (depends on 14)

The display device according to claim 14, wherein the pull-up circuit includes a second transistor and a first capacitor;
a gate electrode of the second transistor is connected to the pull-up node, a first electrode of the second transistor is connected to the first clock signal input terminal and a second electrode of the second transistor is connected to the signal output terminal; and
a first end of the first capacitor is connected to the pull-up node and a second end of the first capacitor is connected to the signal output terminal.

### Claim 17 (depends on 14)

The display device according to claim 14, wherein the reset circuit includes a third transistor and a fourth transistor;
a gate electrode of the third transistor is connected to the reset signal terminal, a first electrode of the third transistor is connected to the pull-down voltage terminal, and a second electrode of the third transistor is connected to the pull-up node; and
a gate electrode of the fourth transistor is connected to the reset signal terminal, a first electrode of the fourth transistor is connected to the pull-down voltage terminal, and a second electrode of the fourth transistor is connected to the signal output terminal.

### Claim 18 (depends on 14)

The display device according to claim 14, wherein the first pull-down control circuit includes a fifth transistor, a sixth transistor, and a seventh transistor;
a gate electrode of the fifth transistor is connected to the second clock signal input terminal, a first electrode of the fifth transistor is connected to the first pull-up voltage terminal and a second electrode of the fifth transistor is connected to the first pull-down node;
a gate electrode of the sixth transistor is connected to the reset signal terminal, a first electrode of the sixth transistor is connected to the first pull-up voltage terminal and a second electrode of the sixth transistor is connected to the first pull-down node; and
a gate electrode of the seventh transistor is connected to the pull-up node, a first electrode of the seventh transistor is connected to the pull-down voltage terminal, and the second electrode of the seventh transistor is connected to the first pull-down node.

### Claim 19 (depends on 14)

The display device according to claim 14, wherein the second pull-down control circuit includes an eighth transistor, a ninth transistor, and a tenth transistor;
a gate electrode of the eighth transistor is connected to the reset signal terminal, a first electrode of the eighth transistor is connected to the second pull-up voltage terminal and a second electrode of the eighth transistor is connected to the second pull-down node;
a gate electrode of the ninth transistor is connected to the second clock signal input terminal, a first electrode of the ninth transistor is connected to the second pull-up voltage terminal and a second electrode of the ninth transistor is connected to the second pull-down node; and
a gate electrode of the tenth transistor is connected to the pull-up node, a first electrode of the tenth transistor is connected to the pull-down voltage terminal, and a second electrode of the tenth transistor is connected to the second pull-down node.

### Claim 20 (depends on 14)

The display device according to claim 14, wherein the first pull-down circuit includes an eleventh transistor and a twelfth transistor;
a gate electrode of the eleventh transistor is connected to the first pull-down node, a first electrode of the eleventh transistor is connected to the pull-down voltage terminal, and a second electrode of the eleventh transistor is connected to the pull-up node; and
a gate electrode of the twelfth transistor is connected to the first pull-down node, a first electrode of the twelfth transistor is connected to the pull-down voltage terminal, and a second electrode of the twelfth transistor is connected to the signal output terminal,
wherein the second pull-down circuit includes a thirteenth transistor and a fourteenth transistor;
a gate electrode of the thirteenth transistor is connected to the second pull-down node, a first electrode of the thirteenth transistor is connected to the pull-down voltage terminal, and a second electrode of the thirteenth transistor is connected to the pull-up node; and
a gate electrode of the fourteenth transistor is connected to the second pull-down node, a first electrode of the fourteenth transistor is connected to the pull-down voltage terminal, and a second electrode of the fourteenth transistor is connected to the signal output terminal.