# US 2018/0025685 A1 · Timing controller, timing control method and display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0025685 A1 - Document ID: US20180025685A1 - Status: Published application - Kind: A1 - Application number: 15/546,999 - Filed: 2016-04-15 - Published: 2018-01-25 - Earliest claimed: 2015-06-25 - Assignees: Boe Technology Group Co., Ltd. - Applicants: BOE Technology Group Co., Ltd. - Inventors: Yanfeng WANG - Web page: https://patentgrep.com/patent/US20180025685A1 ## CPC - G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)} - G09G 3/006: {Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309)} - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/36: using liquid crystals - G09G 3/3208: organic, e.g. using organic light-emitting diodes [OLED] - G09G 2300/0426: Layout of electrodes and connections - G09G 2310/06: Details of flat display driving waveforms - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/02: Improving the quality of display appearance - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A timing controller includes a synchronization module for controlling at least one of a sending time point of a first drive control signal and a sending time point of a second drive control signal, such that the first drive control signal reaches a first driving circuit at the same time point as the second drive control signal reaches a second driving circuit. By controlling the sending time points at which the first drive control signal and the second drive control signal are sent, the two drive control signals are enabled to simultaneously reach the two driving circuits, to achieve the synchronous control of such two driving circuits. The present disclosure relates to a timing controller, a timing control method and a display panel, which make drive control signals synchronously reach two driving circuits that are symmetric with respect to a column-directional center line of a display panel. The timing controller includes a synchronization module for controlling at least one of a sending time point of a first drive control signal and a sending time point of a second drive control signal, such that the first drive control signal reaches a first driving circuit at the same time point as the second drive control signal reaches a second driving circuit. By controlling the sending time points at which the first drive control signal and the second drive control signal are sent, the two drive control signals are enabled to simultaneously reach the two driving circuits, to achieve the synchronous control of such two driving circuits. Display problems may be avoided. ## Claims ### Claim 1 A timing controller comprising: a synchronization module, configured to control at least one of a sending time point of a first drive control signal and a sending time point of a second drive control signal, such that the first drive control signal reaches a first driving circuit at the same time point as the second drive control signal reaches a second driving circuit. ### Claim 2 (depends on 1) The timing controller according to claim 1, wherein the first driving circuit and the second driving circuit are symmetric with respect to a column-directional center line of a display panel comprising the timing controller. ### Claim 3 (depends on 1) The timing controller according to claim 1, wherein the first driving circuit and the second driving circuit are both gate driving circuits, and wherein the first drive control signal and the second drive control signal are both gate start signals or both gate clock signals. ### Claim 4 (depends on 1) The timing controller according to claim 1, wherein the first driving circuit and the second driving circuit are both source driving circuits, and wherein the first drive control signal and the second drive control signal are both data clock signals. ### Claim 5 (depends on 1) The timing controller according to claim 1, wherein the synchronization module comprises: a difference determination sub-module, and a sending time point control sub-module; wherein the difference determination sub-module is configured to determine a transmission time required for a first test signal to be sent from the timing controller to the first driving circuit, a transmission time required for a second test signal to be sent from the timing controller to the second driving circuit, and a difference T1 therebetween; and wherein the sending time point control sub-module is configured to send a drive control signal to a driving circuit corresponding to a longer transmission time earlier by the difference T1 than send a drive control signal to a driving circuit corresponding to a shorter transmission time. ### Claim 6 (depends on 5) The timing controller according to claim 5, wherein the timing controller has a first test signal output terminal, a first test signal return terminal, a second test signal output terminal, and a second test signal return terminal; and wherein the difference determination sub-module is configured to determine transmission times and the difference T1 therebetween, based on a time point at which the first test signal is sent from the first signal output terminal, a time point at which the first test signal is returned to the first test signal return terminal via the first driving circuit, a time point at which the second test signal is sent from the second test signal output terminal, and a time point at which the second test signal is returned to the second test signal return terminal via the second driving circuit. ### Claim 7 (depends on 1) A timing control method for controlling the timing controller according to claim 1, comprising: controlling at least one of a sending time point of a first drive control signal and a sending time point of a second drive control signal, such that the first drive control signal reaches a first driving circuit at the same time point as the second drive control signal reaches a second driving circuit. ### Claim 8 (depends on 7) The method according to claim 7, wherein the first driving circuit and the second driving circuit are symmetric with respect to a column-directional center line of a display panel utilizing the timing control method. ### Claim 9 (depends on 7) The method according to claim 7, wherein the first driving circuit and the second driving circuit are both gate driving circuits, and wherein the first drive control signal and the second drive control signal are both gate start signals or both gate clock signals. ### Claim 10 (depends on 7) The method according to claim 7, wherein the first driving circuit and the second driving circuit are both source driving circuits, and wherein the first drive control signal and the second drive control signal are both data clock signals. ### Claim 11 (depends on 7) The method according to claim 7, wherein the controlling at least one of a sending time point of a first drive control signal and a sending time point of a second drive control signal comprises: determining a transmission time required for a first test signal to be sent from the timing controller to the first driving circuit, a transmission time required for a second test signal to be sent from the timing controller to the second driving circuit, and a difference T1 therebetween; and sending a drive control signal to a driving circuit corresponding to a longer transmission time earlier by the difference T1 than sending a drive control signal to a driving circuit corresponding to a shorter transmission time. ### Claim 12 (depends on 11) The method according to claim 11, wherein the timing controller has a first test signal output terminal, a first test signal return terminal, a second test signal output terminal, and a second test signal return terminal; and wherein transmission times and the difference T1 therebetween are determined, based on a time point at which the first test signal is sent from the first signal output terminal, a time point at which the first test signal is returned to the first test signal return terminal via the first driving circuit, a time point at which the second test signal is sent from the second test signal output terminal, and a time point at which the second test signal is returned to the second test signal return terminal via the second driving circuit. ### Claim 13 (depends on 1) A display panel comprising: the timing controller according to claim 1, and a first driving circuit and a second driving circuit that need to be driven synchronously; wherein the first driving circuit and the second driving circuit are both connected to the timing controller. ### Claim 14 (depends on 13) The display panel according to claim 13, wherein the first driving circuit and the second driving circuit are symmetric with respect to a column-directional center line of the display panel. ### Claim 15 (depends on 13) The display panel according to claim 13, further comprising: a first source printed circuit board and a second source printed circuit board connected to an array substrate of the display panel; wherein the timing controller is provided on the first source printed circuit board or the second source printed circuit board. ### Claim 16 (depends on 13) The display panel according to claim 13, wherein a first test signal output terminal and a first test signal return terminal of the timing controller are both connected to the first driving circuit; and wherein a second test signal output terminal and a second test signal return terminal of the timing controller are both connected to the second driving circuit. ### Claim 17 (depends on 2) The timing controller according to claim 2, wherein the first driving circuit and the second driving circuit are both gate driving circuits, and wherein the first drive control signal and the second drive control signal are both gate start signals or both gate clock signals. ### Claim 18 (depends on 2) The timing controller according to claim 2, wherein the first driving circuit and the second driving circuit are both source driving circuits, and wherein the first drive control signal and the second drive control signal are both data clock signals. ### Claim 19 (depends on 2) The timing controller according to claim 2, wherein the synchronization module comprises: a difference determination sub-module, and a sending time point control sub-module; wherein the difference determination sub-module is configured to determine a transmission time required for a first test signal to be sent from the timing controller to the first driving circuit, a transmission time required for a second test signal to be sent from the timing controller to the second driving circuit, and a difference T1 therebetween; and wherein the sending time point control sub-module is configured to send a drive control signal to a driving circuit corresponding to a longer transmission time earlier by the difference T1 than send a drive control signal to a driving circuit corresponding to a shorter transmission time. ### Claim 20 (depends on 8) The method according to claim 8, wherein the first driving circuit and the second driving circuit are both gate driving circuits, and wherein the first drive control signal and the second drive control signal are both gate start signals or both gate clock signals.