# US 2018/0025105 A1 · Simulating reference voltage response in digital simulation environments > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0025105 A1 - Document ID: US20180025105A1 - Status: Published application - Kind: A1 - Application number: 15/215,757 - Filed: 2016-07-21 - Published: 2018-01-25 - Earliest claimed: 2016-07-21 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: John S. BIALAS, JR.; Siva Pr. BOOSA; Stephen P. GLANCY; Yelena M. TSYRKINA - Web page: https://patentgrep.com/patent/US20180025105A1 ## CPC - G06F 30/3308: using simulation - G06F 30/33: Design verification, e.g. functional simulation or model checking - G06F 30/3312: Timing analysis - G06F 2119/12: Timing analysis or timing optimisation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Embodiments herein describe a digital simulation environment that changes the delay of a digital signal to represent different analog reference voltages. For example, changing the length of time the digital signal is at the logical one state versus the time the digital signal is at the logical zero state may represent an analog reference voltage that is below or above an optimal value. Put differently, the digital simulation environment can insert unequal delay shifts relative to the logical one and zero states of the digital signal to represent different analog voltages. Using these unequal delay shifts, a digital simulation system can test the simulated operation of logic representing a physical system that uses an analog reference voltage as an input to determine if the logic behaves as expected. ## Claims ### Claim 1 A computing system, comprising: at least one computer processor; and a memory storing a program, wherein, when executed by the computer processor, the program is configured to perform an operation comprising: generating a digital simulation environment for testing logic representing a physical system; delaying a digital signal for testing the logic using a first unequal delay shift to represent a first analog reference voltage, wherein the first unequal delay shift changes a duration of a high cycle in the digital signal relative to a duration of a low cycle in the digital signal; receiving updated parameters from the logic in response to providing the digital signal with the first unequal delay shift to the logic; and delaying, based on the updated parameters, the digital signal using a second unequal delay shift to represent a second analog reference voltage different from the first analog reference voltage. ### Claim 2 (depends on 1) The computing system of claim 1, wherein the first and second unequal delay shifts delay at least one of rising edges and falling edges such that the duration of the high cycle is not equal to the duration of the low cycle, and wherein a first ratio between the duration of the high cycle and the duration of the low cycle corresponding to the first unequal delay shift is different than a second ratio between the duration of the high cycle and the duration of the low cycle corresponding to the second unequal delay shift. ### Claim 3 (depends on 1) The computing system of claim 1, wherein the first and second unequal delay shifts comprise an X-state, wherein inserting the X-state into the digital signal changes a ratio between the duration of the high cycle and the duration of the low cycle. ### Claim 4 (depends on 3) The computing system of claim 3, wherein a first duration of the X-state in the digital signal with the first unequal delay shift is different from a second duration of the X-state in the digital signal with the second unequal delay shift. ### Claim 5 (depends on 1) The computing system of claim 1, wherein the logic comprises a reference voltage (VREF) calibration module in a DRAM system, wherein the digital signal is a calibration signal used to test an operation of the VREF calibration module. ### Claim 6 (depends on 5) The computing system of claim 5, wherein the first analog reference voltage represents a first value of VREF that is different from an optimal value of VREF that generates a signal eye with the greatest width. ### Claim 7 (depends on 5) The computing system of claim 5, wherein the operation further comprises: confirming whether the VREF calibration module behaved correctly based on the updated parameters. ### Claim 8 A method, comprising: generating, using one or more computer processors, a digital simulation environment for testing logic representing a physical system; delaying a digital signal for testing the logic using a first unequal delay shift to represent a first analog reference voltage, wherein the first unequal delay shift changes a duration of a high cycle in the digital signal relative to a duration of a low cycle in the digital signal; receiving updated parameters from the logic in response to providing the digital signal with the first unequal delay shift to the logic; and delaying, based on the updated parameters, the digital signal using a second unequal delay shift to represent a second analog reference voltage different from the first analog reference voltage. ### Claim 9 (depends on 8) The method of claim 8, wherein the first and second unequal delay shifts delay at least one of rising edges and falling edges such that the duration of the high cycle is not equal to the duration of the low cycle, and wherein a first ratio between the duration of the high cycle and the duration of the low cycle corresponding to the first unequal delay shift is different than a second ratio between the duration of the high cycle and the duration of the low cycle corresponding to the second unequal delay shift. ### Claim 10 (depends on 8) The method of claim 8, wherein the first and second unequal delay shifts comprise an X-state, wherein inserting the X-state into the digital signal changes a ratio between the duration of the high cycle and the duration of the low cycle. ### Claim 11 (depends on 10) The method of claim 10, wherein a first duration of the X-state in the digital signal with the first unequal delay shift is different from a second duration of the X-state in the digital signal with the second unequal delay shift. ### Claim 12 (depends on 8) The method of claim 8, wherein the logic comprises a reference voltage (VREF) calibration module in a DRAM system, wherein the digital signal is a calibration signal used to test an operation of the VREF calibration module. ### Claim 13 (depends on 12) The method of claim 12, wherein the first analog reference voltage represents a first value of VREF that is different from an optimal value of VREF that generates a signal eye with the greatest width. ### Claim 14 (depends on 12) The method of claim 12, wherein the operation further comprises: confirming whether the VREF calibration module behaved correctly based on the updated parameters. ### Claim 15 A computer program product for testing logic representing a physical system, the computer program product comprising: a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by one or more computer processors to: generate a digital simulation environment for testing the logic; delay a digital signal for testing the logic using a first unequal delay shift to represent a first analog reference voltage, wherein the first unequal delay shift changes a duration of a high cycle in the digital signal relative to a duration of a low cycle in the digital signal; receive updated parameters from the logic in response to providing the digital signal with the first unequal delay shift to the logic; and delay, based on the updated parameters, the digital signal using a second unequal delay shift to represent a second analog reference voltage different from the first analog reference voltage. ### Claim 16 (depends on 15) The computer program product of claim 15, wherein the first and second unequal delay shifts delay at least one of rising edges and falling edges such that the duration of the high cycle is not equal to the duration of the low cycle, and wherein a first ratio between the duration of the high cycle and the duration of the low cycle corresponding to the first unequal delay shift is different than a second ratio between the duration of the high cycle and the duration of the low cycle corresponding to the second unequal delay shift. ### Claim 17 (depends on 15) The computer program product of claim 15, wherein the first and second unequal delay shifts comprise an X-state, wherein inserting the X-state into the digital signal changes a ratio between the duration of the high cycle and the duration of the low cycle. ### Claim 18 (depends on 17) The computer program product of claim 17, wherein a first duration of the X-state in the digital signal with the first unequal delay shift is different from a second duration of the X-state in the digital signal with the second unequal delay shift. ### Claim 19 (depends on 15) The computer program product of claim 15, wherein the logic comprises a reference voltage (VREF) calibration module in a DRAM system, wherein the digital signal is a calibration signal used to test an operation of the VREF calibration module. ### Claim 20 (depends on 19) The computer program product of claim 19, wherein the first analog reference voltage represents a first value of VREF that is different from an optimal value of VREF that generates a signal eye with the greatest width.