# US 2018/0024966 A1 · Autonomous memory architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0024966 A1 - Document ID: US20180024966A1 - Status: Published application - Kind: A1 - Application number: 15/722,624 - Filed: 2017-10-02 - Published: 2018-01-25 - Earliest claimed: 2009-09-11 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Sean Eilert; Mark Leinwander; Jared Hulbert - Web page: https://patentgrep.com/patent/US20180024966A1 ## CPC - G06F 15/17318: {Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An autonomous memory device in a distributed memory sub-system can receive a database downloaded from a host controller. The autonomous memory device can pass configuration routing information and initiate instructions to disperse portions of the database to neighboring die using an interface that handles inter-die communication. Information is then extracted from the pool of autonomous memory and passed through a host interface to the host controller. ## Claims ### Claim 1 A system, comprising: a host interface to couple to a host device; and a distributed array of autonomous memory devices in communication with the host device, each of the autonomous memory devices being formed on a single die and having a microcontroller embedded on the same die as a respective one of the autonomous memory devices to perform computations independently of the host device, the autonomous memory devices being configured to each maintain a routing table to keep track of remaining ones of the autonomous memory devices within the distributed array, each of the autonomous memory devices being further configured to store a latency cost based on a location of the autonomous memory device in communication with the remaining ones of the autonomous memory devices within the distributed array. ### Claim 2 (depends on 1) The system of claim 1, wherein each of the autonomous memory devices includes its own operating system. ### Claim 3 (depends on 1) The system of claim 1, wherein the host device is configured to assign a unique static address to each of the autonomous memory devices. ### Claim 4 (depends on 1) The system of claim 1, wherein the host device is configured to dynamically determine an address of each of the autonomous memory devices during an operation of respective ones of the autonomous memory devices. ### Claim 5 (depends on 1) The system of claim 1, wherein each of the autonomous memory devices is to build the routing table using a scan technique to keep track of remaining ones of the autonomous memory devices within the distributed array. ### Claim 6 (depends on 1) The system of claim 1, wherein each of the autonomous memory devices is configured to store a latency cost based on a location of the autonomous memory devices in communication with another one of the autonomous memory devices. ### Claim 7 (depends on 1) The system of claim 1, wherein each of the autonomous memory devices is configured to execute a search and destroy algorithm simultaneously with others of the autonomous memory devices to isolate and disable an occurrence of a target virus. ### Claim 8 A memory system, comprising a distributed array of autonomous memory devices in communication with a host, each of the autonomous memory devices having a unique address and being formed on a single die including a microcontroller embedded on the same die as a respective one of the autonomous memory devices, the microcontroller of each die having its own operating system, the devices in the memory array having a first interface to communicate with the host and at least one second interface to communicate with others of the devices in the distributed array. ### Claim 9 (depends on 8) The memory system of claim 8, further comprising a memory within each of the autonomous memory devices to store information about how a host database is organized. ### Claim 10 (depends on 9) The memory system of claim 9, wherein each of the microcontrollers is configured to perform computations on at least portions of the database and return results of the computations to the host. ### Claim 11 (depends on 8) The system of claim 8, wherein the second interfaces are configured to transfer messages that contain a command and a list of parameters to others of the memory devices. ### Claim 12 (depends on 11) The system of claim 11, wherein the messages include a transfer of data, address information that refers to data in the distributed array, and object identifiers that reference an object located in the distributed array. ### Claim 13 A system, comprising: a distributed array of autonomous memory devices, each of the devices having a host interface to communicate with a host controller, each of the autonomous memory devices having a unique address and being formed on a single die including a microcontroller embedded on the same die as a respective one of the autonomous memory devices; a memory in the autonomous memory devices, at least some of the memory devices to receive a database through the host interface from the host controller and to store the database in the memory of the memory device, the microcontroller within the at least some of the memory devices to disperse portions of the database to neighboring remaining ones of the autonomous memory devices through inter-die communication ports within the autonomous memory devices. ### Claim 14 (depends on 13) The system of claim 13, wherein the memory in at least one of the memory devices is to receive software from the host controller to allow the at least one autonomous memory device to control other ones of the autonomous memory devices. ### Claim 15 (depends on 13) The system of claim 13, wherein each of the autonomous memory devices is configured to parse and execute operations autonomously within selected ones of the memory devices. ### Claim 16 (depends on 15) The system of claim 15, wherein the selected ones of the memory devices are further configured to accumulate and report results from the executed operations to the host controller when the operations are complete. ### Claim 17 (depends on 13) The system of claim 13, wherein selected ones of the memory devices are configured to execute stored routines, provided by libraries and stored within respective ones of the memories, to build applications. ### Claim 18 (depends on 13) The system of claim 13, further comprising acceleration hardware within each of the autonomous memory devices. ### Claim 19 (depends on 13) The system of claim 13, wherein each of the autonomous memory devices has multiple inter-die communication ports to communicate simultaneously with each of multiple nearest-neighbor ones of remaining ones of the memory devices. ### Claim 20 (depends on 13) The system of claim 13, wherein each of the autonomous memory devices has at least one autonomous memory management mechanism selected from mechanisms including a wear leveling mechanism, an error detection and correction mechanism, and a compression and decompression mechanism.