# US 2018/0024965 A1 · Image processing apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0024965 A1 - Document ID: US20180024965A1 - Status: Published application - Kind: A1 - Application number: 15/653,630 - Filed: 2017-07-19 - Published: 2018-01-25 - Earliest claimed: 2016-07-20 - Assignees: Canon Kabushiki Kaisha - Applicants: Canon Kabushiki Kaisha - Inventors: Jun Suzuki - Web page: https://patentgrep.com/patent/US20180024965A1 ## CPC - G06F 15/163: Interprocessor communication - G06F 1/32: Means for saving power - G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality - G06F 1/3287: by switching off individual functional units in the computer system - G06F 1/3293: by switching to a less power-consuming processor, e.g. sub-CPU - G06F 3/0634: {by changing the state or mode of one or more devices} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract An image processing apparatus includes a plurality of image processors, and is capable of providing an instruction of any one of a plurality of operation modes including a first recording mode. In the first recording mode, among the plurality of image processors, each image processor other than an image processor in a final stage performs predetermined image processing on image data of a portion that needs to be processed, and outputs image data of a portion other than the portion that needs to be processed to an image processor in a subsequent stage without performing the predetermined image processing thereon. One of the plurality of image processors that is set as a power supply master performs control so as to sequentially bring the plurality of image processors into a power supply state corresponding to the operation mode indicated by the instruction. ## Claims ### Claim 1 An image processing apparatus comprising: an imaging unit; a plurality of serially connected image processors, wherein one of the plurality of image processors that is in a first stage is connected to the imaging unit; a recording unit that records image data processed by the plurality of image processors in a storage medium; and a mode instruction unit that provides an instruction of one of a plurality of operation modes including a first recording mode in which each of the plurality of image processors performs predetermined image processing on a portion of image data output from the imaging unit, wherein in the first recording mode, an image processor other than an image processor in a final stage among the plurality of image processors performs the predetermined image processing on image data of a portion that needs to be processed by the image processor, and outputs image data of a portion other than the portion that needs to be processed by the image processor to an image processor in a subsequent stage without performing the predetermined image processing thereon; and a power supply unit that supplies power to the plurality of image processors, wherein the plurality of image processors each include a plurality of function blocks, and individually control a power supply state of the plurality of function blocks, one of the plurality of image processors is set as a power supply master, and the image processor that has been set as the power supply master performs control so as to sequentially bring the plurality of image processors into the power supply state corresponding to the operation mode indicated by the mode instruction unit. ### Claim 2 (depends on 1) The image processing apparatus according to claim 1, wherein the mode instruction unit is connected to one of the plurality of image processors, and the image processor connected to the mode instruction unit is set as the power supply master. ### Claim 3 (depends on 2) The image processing apparatus according to claim 2, wherein the mode instruction unit is connected to the image processor in the first stage. ### Claim 4 (depends on 1) The image processing apparatus according to claim 1, wherein the plurality of image processors bring function blocks required for the operation mode indicated by the instruction provided by the mode instruction unit into a power ON state, and bring function blocks other than the function blocks required for the operation mode indicated by the instruction into a power save state. ### Claim 5 (depends on 1) The image processing apparatus according to claim 1, wherein the image processor that has been set as the power supply master changes an order of the image processors that are brought into a power supply state corresponding to the indicated operation mode according to the operation mode indicated by the instruction. ### Claim 6 (depends on 1) The image processing apparatus according to claim 1, wherein an external apparatus is connected to one of the plurality of image processors, the external apparatus outputs a signal for providing an instruction of an operation mode of the image processing apparatus, and when the image processing apparatus is operated in the operation mode indicated by the instruction provided by the external apparatus instead of the mode instruction unit, the image processor connected to the external apparatus is set as the power supply master. ### Claim 7 (depends on 1) The image processing apparatus according to claim 1, wherein when the first recording mode is indicated by the mode instruction unit, the image processor that has been set as the power supply master performs control so as to bring the plurality of image processors into the power supply state corresponding to the first recording mode sequentially from the image processor in the first stage to the image processor in the final stage. ### Claim 8 (depends on 1) The image processing apparatus according to claim 1, wherein the plurality of modes include a reproduction mode in which image data is reproduced from the storage medium, the recording unit is connected to the image processor in the final stage among the plurality of image processors, and a display apparatus is connected to one of the plurality of image processors, and when the reproduction mode is indicated by the mode instruction unit, the image processor that has been set as the power supply master performs control so as to bring the plurality of image processors into the power supply state corresponding to the reproduction mode sequentially from the image processor in the final stage to the image processor connected to the display apparatus. ### Claim 9 (depends on 1) The image processing apparatus according to claim 1, wherein in response to the mode instruction unit providing the instruction of the operation mode, the image processor that has been set as the power supply master transmits information indicative of the operation mode indicated by the instruction sequentially to image processors other than the power supply master, and each of the image processors other than the power supply master changes the power supply state of the plurality of function blocks of the image processor according to the information indicative of the operation mode transmitted from the image processor that has been set as the power supply master. ### Claim 10 (depends on 1) The image processing apparatus according to claim 1, wherein each of the plurality of image processors stores information indicative of image processors that are set as the power supply master in the plurality of operation modes. ### Claim 11 (depends on 1) The image processing apparatus according to claim 1, wherein each of the plurality of image processors is configured as a single-chip semiconductor integrated circuit.