# US 2018/0024959 A1 · Mobile computing device reconfiguration is response to environmental factors including downloading hardware and software associated with multiple users of the mobile device

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- Number: US 2018/0024959 A1
- Document ID: US20180024959A1
- Status: Published application
- Kind: A1
- Application number: 15/712,169
- Filed: 2017-09-22
- Published: 2018-01-25
- Earliest claimed: 2011-10-11
- Assignees: Etron Technology, Inc.
- Applicants: Etron Technology, Inc.
- Inventors: Weng-Dah Ken; Chao-Chun Lu; Jan-Mye Sung
- Web page: https://patentgrep.com/patent/US20180024959A1

## CPC

- G06F 13/4234: {being a memory bus}
- G06F 13/4018: {with data-width conversion}
- G06F 13/42: Bus transfer protocol, e.g. handshake; Synchronisation
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 90/00: Package configurations
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/301: {for alignment}
- H10W 46/601: {for use after dicing}
- H10W 72/07254: {changes in dispositions}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus.

## Claims

### Claim 1

A reconfigurable high speed memory chip module, comprising:
a plurality of memory cell arrays, wherein each of the plurality of memory cell arrays comprises multiple memory cell array integrated circuits (ICs);
a first transmission bus coupled to the plurality of memory cell arrays; and
a logic unit coupled to the first transmission bus for accessing the plurality of memory cell arrays through the first transmission bus;
wherein at least one through silicon via (TSV) exists within a non-active circuit region surrounding or partially surrounding an active circuit region of at least one of the logic unit and each of the memory cell array ICs.

### Claim 2 (depends on 1)

The reconfigurable high speed memory chip module of claim 1, wherein the first transmission bus has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, and the first transmission bus is used for transmitting a first set of parallel data along with the multiple memory cell array ICs, wherein bus width of the first transmission bus is wider than bus width of an input/output (I/O) data bus of each of the memory cell array ICs.

### Claim 3 (depends on 1)

The reconfigurable high speed memory chip module of claim 1, further comprising:
a second transmission bus coupled to the logic unit having a second programmable data width and a second programmable address width, and the first transmission bus has a first programmable data width and a first programmable address width.

### Claim 4 (depends on 3)

The reconfigurable high speed memory chip module of claim 3, wherein the first programmable transmitting or receiving data rate, the first programmable transmitting or receiving signal swing, the first programmable data width, and the first programmable address width have first predetermined values, and the second programmable transmitting or receiving data rate, the second programmable transmitting or receiving signal swing, the second programmable data width, and the second programmable address width have second predetermined values.

### Claim 5 (depends on 3)

The reconfigurable high speed memory chip module of claim 3, wherein programmability of the first transmission bus or the second transmission bus corresponds to a one-time programming (OTP), a multi-time programming (MTP), a Flash Memory, an embedded memory, an anti-fuse, a register, firmware, or software.

### Claim 6 (depends on 1)

The reconfigurable high speed memory chip module of claim 1, wherein the at least one through silicon via (TSV) exists within the non-active circuit region surrounding or partially surrounding the active circuit region of the each of the memory cell array ICs, and the active circuit region of the each of the memory cell array ICs is used for forming at least one active device of the each of the memory cell array ICs.

### Claim 7 (depends on 6)

The reconfigurable high speed memory chip module of claim 6, wherein the at least one TSV is used for connecting to a power or a ground supply.

### Claim 8 (depends on 6)

The reconfigurable high speed memory chip module of claim 6, wherein the non-active circuit region of the each of the memory cell array ICs has a width less than about 50 um.

### Claim 9 (depends on 6)

The reconfigurable high speed memory chip module of claim 6, wherein the at least one TSV has a width less than about 20 um.

### Claim 10 (depends on 6)

The reconfigurable high speed memory chip module of claim 6, wherein a corner of one of the memory cell array ICs has an orientation identification mark wherein the orientation identification mark is formed by a process comprising Laser step.

### Claim 11 (depends on 6)

The reconfigurable high speed memory chip module of claim 6, wherein a corner of one of the memory cell array ICs has an orientation identification mark wherein the orientation identification mark comprises at least one of an edge cut, a line of drawing, two lines of drawing, a hole, or an arbitrary pattern.

### Claim 12 (depends on 1)

The reconfigurable high speed memory chip module of claim 1, wherein the at least one TSV exists within the non-active circuit region surrounding or partially surrounding the active circuit region of the logic unit, and the active circuit region of the logic unit is used for forming at least one active device of the logic unit, wherein the at least one TSV is used for connecting to a power or a ground supply.

### Claim 13 (depends on 12)

The reconfigurable high speed memory chip module of claim 12, wherein the logic unit comprises a TSV to connect to one of the multiple memory cell array ICs and further comprises a wire bonding pad to connect to another IC with function being characterized with an analog function, a digital signal processing (DSP) function, a communication function, a wireless fidelity (Wi-Fi) function, a power management function, a mix-mode function, an RF function, or a micro electro mechanical systems (MEMS) function.

### Claim 14 (depends on 12)

The reconfigurable high speed memory chip module of claim 12, wherein the non-active circuit region of the logic unit has a width less than about 50 um.

### Claim 15 (depends on 12)

The reconfigurable high speed memory chip module of claim 12, wherein the at least one TSV has a width less than about 20 um.

### Claim 16 (depends on 1)

The reconfigurable high speed memory chip module of claim 1, wherein at least one pair of TSVs exist in neighboring within the non-active circuit region surrounding or partially surrounding the active circuit region of the each of the memory cell array ICs, and wherein the at least one pair of TSVs are used for connecting to a power or a ground supply.

### Claim 17 (depends on 6)

The reconfigurable high speed memory chip module of claim 6, wherein a corner of one of the memory cell array ICs has an identification mark wherein the identification mark is formed by a process comprising a TSV step.

### Claim 18 (depends on 1)

The reconfigurable high speed memory chip module of claim 1, wherein at least one pair of TSVs exist in neighboring within the non-active circuit region surrounding or partially surrounding the active circuit region of the logic unit, and wherein the at least one pair of TSVs are used for connecting to a power or a ground supply.

### Claim 19 (depends on 1)

The reconfigurable high speed memory chip module of claim 1, wherein a dicing method for at least one memory cell array IC of the multiple memory cell array ICs comprises a laser process.

### Claim 20 (depends on 1)

The reconfigurable high speed memory chip module of claim 1, wherein a dicing method for the logic unit comprises a laser process.

### Claim 21

An electronic system device with a high speed memory chip module, the electronic system device comprising:
an ASIC processor;
a plurality of memory cell arrays, wherein each of the plurality of memory cell arrays comprises multiple memory cell array ICs;
a first transmission bus coupled to the plurality of memory cell arrays; and
a logic unit coupled to the ASIC processor and the first transmission bus for accessing the plurality of memory cell arrays through the first transmission bus;
wherein at least one through silicon via (TSV) exists within a non-active circuit region surrounding or partially surrounding an active circuit region of at least one of the logic unit and each of the memory cell array ICs.

### Claim 22 (depends on 21)

The electronic system device of claim 21, wherein the first transmission bus has a first programmable transmitting or receiving data rate, and a first programmable transmitting or receiving signal swing corresponding to the firmware or the software comprised in the ASIC processor.

### Claim 23 (depends on 21)

The electronic system device of claim 21, further comprising:
a second transmission bus has a second programmable data width and a second programmable address width associated to the firmware or the software, and the first transmission bus has a first programmable data width and a first programmable address width associated to the firmware or the software.

### Claim 24 (depends on 23)

The electronic system device of claim 23, wherein the programmability of the first transmission bus and the second transmission bus are associated with an OTP, an MTP, a Flash Memory, an embedded memory, an anti-fuse memory, a register, the firmware or the software.