# US 2018/0024951 A1 · Heterogeneous multi-processor device and method of enabling coherent data access within a heterogeneous multi-processor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0024951 A1 - Document ID: US20180024951A1 - Status: Published application - Kind: A1 - Application number: 15/213,875 - Filed: 2016-07-19 - Published: 2018-01-25 - Earliest claimed: 2016-07-19 - Assignees: Freescale Semiconductor, Inc. - Applicants: Freescale Semiconductor, Inc. - Inventors: Graham Edmiston - Web page: https://patentgrep.com/patent/US20180024951A1 ## CPC - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 3/0613: {in relation to throughput} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0683: {Plurality of storage devices} - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A heterogeneous multi-processor device having a first processor component arranged to issue a data access command request, a second processor component arranged to execute a set of threads, a task scheduling component arranged to schedule the execution of threads by the second processor component, and an internal memory component. In response to the data access command request being issued by the first processor component, the task scheduling component is arranged to wait for activities relating to the indicated subset of threads to finish, and when the activities relating to the indicated subset of threads have finished to load a command thread for execution by the second processor component, the command thread being arranged to cause the second processor component to read the indicated data from the at least one region of memory and make the read data available to the first processor component. ## Claims ### Claim 1 A heterogeneous multi-processor device comprising: a first processor component; a second processor component arranged to execute a set of threads; a task scheduling component arranged to schedule the execution of threads by the second processor component; and an internal memory component, wherein: the first processor component is arranged to issue a data access command request, and to output an indication of data stored within at least one region of memory to be accessed and an indication of a subset of the set of threads associated with the data to be accessed; and in response to the data access command request being issued by the first processor component, the task scheduling component is arranged to wait for activities relating to the indicated subset of threads to finish, and when the activities relating to the indicated subset of threads have finished to load a command thread for execution by the second processor component, the command thread being arranged to cause the second processor component to read the indicated data from the at least one region of memory and make the read data available to the first processor component. ### Claim 2 (depends on 1) The heterogeneous multi-processor device of claim 1, wherein the command thread is arranged to cause the second processor component to issue a direct memory access to retrieve at least a part of the indicated data from external memory. ### Claim 3 (depends on 1) The heterogeneous multi-processor device of claim 1, wherein, in response to the data access command request being issued by the first processor component, the task scheduling component is further arranged to mask the indicated subset of threads from being loaded for execution by the second processor component. ### Claim 4 (depends on 3) The heterogeneous multi-processor device of claim 3, wherein the task scheduling component is further arranged to unmask the indicated subset of threads in response to an indication from the second processor component that the indicated data has been read. ### Claim 5 (depends on 1) The heterogeneous multi-processor device of claim 1, wherein the task scheduling component is further arranged to clear the data access command request upon the indicated data being made available to the first processor. ### Claim 6 (depends on 1) The heterogeneous multi-processor device of claim 1, wherein, in response to the data access command request being issued by the first processor component, the task scheduling component is arranged to wait for executing tasks of threads within the indicated subset of threads to finish and for direct memory accesses issued by threads within the indicated subset of threads to complete before loading the command thread for execution by the second processor component. ### Claim 7 (depends on 1) The heterogeneous multi-processor device of claim 1, wherein the command thread is further arranged to cause the second processor component to overwrite the indicated data after it has read the indicated data. ### Claim 8 (depends on 1) The heterogeneous multi-processor device of claim 1, wherein the command thread is arranged to cause the second processor component to copy the indicated data to a region of memory accessible by the first processor component. ### Claim 9 (depends on 1) The heterogeneous multi-processor device of claim 1, wherein the first processor component is arranged to output the indication of the data to be accessed within a data field of a command request register, and to issue the data access command request by setting an enable bit within the command request register. ### Claim 10 (depends on 1) The heterogeneous multi-processor device of claim 1, wherein the first processor component is arranged to output the indication of the subset of threads by setting a respective bit within a thread array register corresponding to each thread within the subset of threads. ### Claim 11 A method of enabling coherent data access within a heterogeneous multi-processor device; the method comprising: receiving an indication of a data access command request being issued by a first processor component; determining a subset of threads associated with data to be accessed, the subset of threads being arranged to execute on a second processor component; waiting for activities relating to the determined subset of threads to finish; when the activities relating to the determined subset of threads have finished, causing the second processor component to read data from at least one region of memory and make the read data available to the first processor component. ### Claim 12 (depends on 11) The method of claim 11 further comprising causing the second processor component to issue a direct memory access to retrieve at least a part of the date from an external memory, wherein the at least a part of the data to be read is stored within at least one region of external memory. ### Claim 13 (depends on 11) The method of claim 11 further comprising, in response to receiving the indication of the data access command request being issued by the first processor component, masking the determined subset of threads from being loaded for execution by the second processor component. ### Claim 14 (depends on 13) The method of claim 13 further comprising unmasking the determined subset of threads in response to receiving an indication from the second processor component that the data has been read. ### Claim 15 (depends on 11) The method of claim 11 comprising, in response to receiving the indication of the data access command request being issued by the first processor component and before causing the second processor component to read data from at least one region of memory and make the read data available to the first processor component, waiting for executing tasks of threads within the determined subset of threads to finish and for direct memory accesses issued by threads within the determined subset of threads to complete. ### Claim 16 (depends on 11) The method of claim 11 further comprising causing the second processor component to overwrite the data in memory after reading the data. ### Claim 17 (depends on 11) The method of claim 11, wherein the method comprises causing the second processor component to copy the indicated data to a region of memory accessible by the first processor component. ### Claim 18 (depends on 11) The method of claim 11, wherein the method comprises the first processor component providing an indication of the data to be accessed within a data field of a command request register, and issuing the data access command request by setting an enable bit within the command request register. ### Claim 19 (depends on 11) The method of claim 11, wherein the method comprises the first processor component providing an indication of the subset of threads by setting a respective bit within a thread array register corresponding to each thread within the subset of threads.