# US 2018/0024950 A1 · Ring bus architecture for use in a memory module

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- Number: US 2018/0024950 A1
- Document ID: US20180024950A1
- Status: Published application
- Kind: A1
- Application number: 15/716,046
- Filed: 2017-09-26
- Published: 2018-01-25
- Earliest claimed: 2014-12-29
- Assignees: SanDisk Technologies LLC
- Applicants: SanDisk Technologies LLC
- Inventors: Alan Welsh Sinclair
- Web page: https://patentgrep.com/patent/US20180024950A1

## CPC

- G06F 13/1684: {using multiple buses}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 13/287: {Multiplexed DMA (G06F13/30 takes precedence)}
- G06F 13/4068: {Electrical coupling}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Ring bus architectures for use in a memory module are disclosed. A memory module may include a primary ring bus; a ring bus controller positioned on the primary ring bus; a secondary ring bus in communication with the primary ring bus via a first bus bridge; and a tertiary ring bus in communication with the secondary ring bus via a second bus bridge. The ring bus controller is configured to direct the first bus bridge to route data between the primary ring bus and the secondary ring bus and is configured to direct the second bus bridge to route data between the secondary ring bus and the tertiary ring bus.

## Claims

### Claim 1

A memory module comprising:
a primary ring bus;
a ring bus controller positioned on the primary ring bus;
a first secondary ring bus in communication with the primary ring bus via a first bus bridge;
a second secondary ring bus in communication with the primary ring bus via a second bus bridge; and
a tertiary ring bus in communication with the first secondary ring bus via a third ring bus bridge and in communication with the second secondary ring bus via a fourth ring bus bridge;
wherein the ring bus controller is configured to direct the third bus bridge and the fourth bus bridge to route data between the first secondary ring bus and the second secondary ring bus over the tertiary ring bus without routing data over the primary ring bus.

### Claim 2 (depends on 1)

The memory module of claim 1, wherein the ring bus controller is configured to:
send a command to at least the third ring bus bridge and the fourth ring bus bridge to configure the third ring bus bridge and the fourth ring bus bridge to route data between the first secondary ring bus and the tertiary ring bus via the tertiary ring bus.

### Claim 3 (depends on 1)

The memory module of claim 1, wherein the ring bus controller is configured to monitor data traffic on the primary ring bus, the first secondary ring bus, the second secondary ring bus, and the tertiary ring bus.

### Claim 4 (depends on 3)

The memory module of claim 3, wherein the ring bus controller is configured to send a command to at least one of the first bus bridge, the second bus bridge, the third bus bridge, or the fourth bus bridge to adjust routing of data along one or more of the primary ring bus, the first secondary ring bus, the second secondary ring bus, or the tertiary ring bus based on a volume of traffic on the primary ring bus, the first secondary ring bus, the second secondary ring bus, and the tertiary ring bus

### Claim 5 (depends on 1)

The memory module of claim 1, further comprising:
an encryption engine positioned on the tertiary ring bus; and
an error correction code engine positioned on the tertiary ring bus.

### Claim 6 (depends on 5)

The memory module of claim 5, wherein the ring bus controller is configured to direct the third bus bridge and the fourth bus bridge to route data from the first secondary ring bus to at least one of the encryption engine or the error correction code engine positioned on the tertiary ring bus without routing the data over the primary ring bus.

### Claim 7

A memory module comprising:
a primary ring bus;
a first secondary ring bus in communication with the primary ring bus via a first bus bridge;
a second secondary ring bus in communication with the primary ring bus via a second bus bridge; and
a tertiary ring bus in communication with the first secondary ring bus via a third ring bus bridge and in communication with the second secondary ring bus via a fourth ring bus bridge;
means for directing the third bus bridge and the fourth bus bridge to route data between the first secondary ring bus and the second secondary ring bus over the tertiary ring bus without routing data over the primary ring bus.

### Claim 8 (depends on 7)

The memory module of claim 7, further comprising means for sending a command to at least the third ring bus bridge and the fourth ring bus bridge to configure the third ring bus bridge and the fourth ring bus bridge to route data between the first secondary ring bus and the tertiary ring bus via the tertiary ring bus.

### Claim 9 (depends on 7)

The memory module of claim 7, further comprising means for monitoring data traffic on the primary ring bus, the first secondary ring bus, the second secondary ring bus, and the tertiary ring bus.

### Claim 10 (depends on 9)

The memory module of claim 9, further comprising means for sending a command to at least one of the first bus bridge, the second bus bridge, the third bus bridge, and the fourth bus bridge to adjust routing of data along one or more of the primary ring bus, the first secondary ring bus, the second secondary ring bus, and the tertiary ring bus based on a volume of traffic on the primary ring bus, the first secondary ring bus, the second secondary ring bus, and the tertiary ring bus.

### Claim 11 (depends on 7)

The memory module of claim 7, further comprising:
an encryption engine positioned on the tertiary ring bus; and
an error correction code engine positioned on the tertiary ring bus.

### Claim 12 (depends on 11)

The memory module of claim 11, further comprising means for directing the third bus bridge and the fourth bus bridge to route data from the first secondary ring bus to at least one of the encryption engine or the error correction code engine positioned on the tertiary ring bus without routing the data over the primary ring bus.

### Claim 13

A memory module comprising:
a primary ring bus;
a first secondary ring bus in communication with the primary ring bus;
a second secondary ring bus in communication with the primary ring bus:
a tertiary ring bus in communication with the first secondary ring bus and the second secondary ring bus; and
means for routing data between the first secondary ring bus and the second secondary ring bus over the tertiary ring bus without routing data over the primary ring bus.

### Claim 14 (depends on 13)

The memory module of claim 13, further comprising means for monitoring data traffic on the primary ring bus, the first secondary ring bus, the second secondary ring bus, and the tertiary ring bus.

### Claim 15 (depends on 14)

The memory module of claim 14, further comprising means for adjusting a routing of data along the primary ring bus, the first secondary ring bus, the second secondary ring bus, and the tertiary ring bus based on a volume of traffic on the primary ring bus, the first secondary ring bus, the second secondary ring bus, and the tertiary ring bus.