# US 2018/0024945 A1 · Context-based protection system

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- Number: US 2018/0024945 A1
- Document ID: US20180024945A1
- Status: Published application
- Kind: A1
- Application number: 15/653,203
- Filed: 2017-07-18
- Published: 2018-01-25
- Earliest claimed: 2016-07-19
- Assignees: Cypress Semiconductor Corporation
- Applicants: Cypress Semiconductor Corporation
- Inventors: Jan-Willem Van de Waerdt; Kai Dieffenbach; Uwe Moslehner; Jens Wagner; Mathias Sedner; Venkat NATARAJAN
- Web page: https://patentgrep.com/patent/US20180024945A1

## CPC

- G06F 12/1491: {in a hierarchical protection system, e.g. privilege levels, memory rings}
- G06F 12/1441: {for a range}
- G06F 12/145: {the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism}
- G06F 12/1458: {by checking the subject access rights}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F 21/572: {Secure firmware programming, e.g. of basic input output system [BIOS]}
- G06F 21/76: in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F 2212/1052: Security improvement
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A context-based protection system uses tiered protection structures including master protection units, shared memory protection units, a peripheral protection units to provide security to bus transfer operations between central processing units (CPUs), memory array or portions of arrays, and peripherals.

## Claims

### Claim 1

A. system comprising:
a first central processing unit (CPU) configurable to operate in a plurality of protection contexts; and
at least one peripheral module, the peripheral module accessible by the first CPU when the first CPU is configured in a first protection context of the plurality of protection contexts and inaccessible by the first CPU when the first CPU is configured in a second protection context of the plurality of protection contexts.

### Claim 2 (depends on 1)

The system of claim 1, further comprising a CPU subsystem the CPU subsystem comprising:
the first CPU;
at least one memory protection unit; and
at least one shared memory protection unit.

### Claim 3 (depends on 2)

The system of claim 2, wherein the at least memory protection unit differentiates between user and privileged accesses from a single bus mater.

### Claim 4 (depends on 2)

The system f claim 2, wherein the at least one shared memory protection unit differentiates between the first and second protection contexts of the plurality of protection contexts and differentiates between secure and non-secure accesses of the first CPU,

### Claim 5 (depends on 1)

The system of claim 1, further comprising a peripheral subsystem comprising:
the at least one peripheral module; and
at least one peripheral protection unit, wherein the at least one peripheral protection unit differentiates between:
the first and second protection contexts of the plurality of protection contexts,
secure and non-secure accesses, and
user mode accesses from privileged mode accesses.

### Claim 6 (depends on 1)

The system of claim 1, wherein access to the peripheral module is controlled by values of vector pairs, the first vector of the vector pair for controlling read access to the peripheral module and the second vector of the vector pair for controlling write access to the first vector of the vector pair.

### Claim 7 (depends on 1)

The system of claim 1, wherein the first CPU operation in the second protection context from the first protection context is gated by an interrupt factor associated with the second protection context.

### Claim 8 (depends on 1)

The system of claim 1, wherein the peripheral module is a memory.

### Claim 9 (depends on 1)

The system of claim 1, further comprising a second CPU configurable to operate in at least one of the plurality of protection contexts.

### Claim 10

A bus infrastructure comprising a plurality of protection structures, the plurality of protection structures comprising:
a memory protection unit (MPU) assigned to a single bus master, the MPU to differentiate user and privileged accesses from the bus master;
a shared memory protection unit (SMPU) assigned to a plurality of bus bus masters, the SMPU to differentiate between different protection contexts and to differentiate between secure and non-secure access to a memory; and
a peripheral protection unit (PPU) assigned with a peripheral group, the PPU to differentiate secure and non-secure accesses to the peripheral group.

### Claim 11 (depends on 10)

The bus infrastructure of claim 10, wherein the PPU differentiates between secure and non-secure accesses to the peripheral group by acknowledging a user mode and a privileged mode, wherein access permitted in a user mode is different than access permitted in a privileged mode,

### Claim 12 (depends on 10)

The bus infrastructure of claim 10, wherein each of the plurality of protection structures are defined by:
an address region; and
access control attributes, wherein the access control attributes specify access control to memory location.

### Claim 13 (depends on 10)

The bus infrastructure of claim 10, wherein the PPU comprises a plurality of protection regions, including at least one of:
all peripherals in the peripheral group; and
a subset of peripherals of the peripheral group, including individual interprocessor communication (RC) structures, DMA controller channel structures, SMPU protection-required structures, or PPU protection region structures.

### Claim 14 (depends on 10)

The bus infrastructure of claim 10, wherein the bus master is a central processing unit (CPU) operating in a first protection context and a second protection context.

### Claim 15 (depends on 14)

The bus infrastructure of claim 14, wherein the bus master accesses the peripheral group when the CPU operates in the first protection context and is be prohibited from accessing the peripheral group when the CPU operates in the second protection context.

### Claim 16 (depends on 10)

The bus infrastructure of claim 10, wherein access to the peripheral group is controlled by values of vector pairs of the PPU, the first vector of the vector pair for controlling read access to the peripheral group and the second vector of the vector pair for controlling write access to the first vector of the vector pair.

### Claim 17

A method for controlling access to peripheral modules, the method comprising:
comparing a first protection context of a plurality of protection contexts of a central processing unit (CPU) to an allowed protection context of a first peripheral module;
permitting access to the first peripheral module by the CPU if the first protection context of the CPU matches the allowed protection context of the first peripheral module;
altering the protection context of the CPU from the first protection context to a second protection context;
prohibiting access to the first peripheral module by the CPU if the second protection context does not match the allowed protection context of the first peripheral module; and
permitting access to a second peripheral module by the CPU if the second protection context of the CPU matches the allowed protection context of the second peripheral module, wherein the first protection context is different from the second protection context.

### Claim 18 (depends on 17)

The method for context-based protection of peripheral modules of claim 17, wherein access to the peripheral modules is defined by a vector pair for each peripheral module, and wherein the vector pair comprises a first vector of the vector pair for controlling read access to the peripheral module and a second vector of the vector pair for controlling write access to the first vector of the vector pair.