# US 2018/0024938 A1 · Allocating physical pages to sparse data sets in virtual memory without page faulting

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- Number: US 2018/0024938 A1
- Document ID: US20180024938A1
- Status: Published application
- Kind: A1
- Application number: 15/216,071
- Filed: 2016-07-21
- Published: 2018-01-25
- Earliest claimed: 2016-07-21
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: Timour T. Paltashev; Christopher Brennan
- Web page: https://patentgrep.com/patent/US20180024938A1

## CPC

- G06F 12/1009: using page tables, e.g. page table structures
- G06F 12/023: {Free address space management}
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 12/128: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
- G06F 2212/1044: Space efficiency improvement
- G06F 2212/657: Virtual address space management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A processing system for reduction of a virtual memory page fault rate that includes a first memory to store a dataset, a second memory to store a subset of the dataset, and a processing unit. The processing unit is configured to receive a memory access request including a virtual address and determine whether the virtual address is mapped to a first physical page in the first memory and or a second physical page in the second memory. The processing unit maps a third physical page in a free page pool of the second memory to the virtual address in response to the virtual address not being mapped to the second physical page. The processing unit also grants access to the third physical page that is mapped to the virtual address.

## Claims

### Claim 1

A method for reduction of a virtual memory page fault rate in a system that includes a first memory to store a dataset and a second memory to store a subset of the dataset, the method comprising:
receiving a memory access request including a virtual address;
map a first physical page in a free page pool of the second memory to the virtual address in response to the virtual address not being mapped to a second physical page in the second memory; and
granting the memory access request to the first physical page.

### Claim 2 (depends on 1)

The method of claim 1, wherein the memory access request is a request to write to the virtual address, and wherein mapping the first physical page to the virtual address comprises initializing the first physical page to a known state.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
writing information to the first physical page on the basis of the virtual address.

### Claim 4 (depends on 1)

The method of claim 1, wherein the memory access request is a request to read information stored at the virtual address, and the method further comprises:
spawning a process to generate the information that is to be read in response to the memory access request;
writing the generated information to the first physical page on the basis of the virtual address; and
reading the generated information from the first physical page.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
allocating a plurality of physical pages including the first physical page to the free page pool.

### Claim 6 (depends on 5)

The method of claim 5, wherein mapping the first physical page to the virtual address comprises removing the first physical page from the free page pool.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
determining a number of physical pages in the free page pool;
unmapping at least one physical page from at least one corresponding virtual address in response to the number being less than a threshold; and
adding the at least one unmapped physical page to the free page pool.

### Claim 8 (depends on 1)

The method of claim 1, wherein receiving the memory access request comprises receiving the memory access request in response to the virtual address missing entries in at least one address translation buffer associated with at least one cache that is configured to cache information stored in the second memory.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
updating a page table to indicate the mapping of the virtual address to the third physical page.

### Claim 10

An apparatus comprising:
a first memory to store a dataset;
a second memory to store a subset of the dataset; and
a processing unit configured to:
receive a memory access request including a virtual address;
map a first physical page in a free page pool of the second memory to the virtual address in response to the virtual address not being mapped to a second physical page in the second memory; and
grant the memory access request to the first physical page.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the memory access request is a request to write to the virtual address, and wherein the processing unit is configured to initialize the first physical page to a known state.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the processing unit is configured to write information to the first physical page on the basis of the virtual address.

### Claim 13 (depends on 10)

The apparatus of claim 10, wherein the memory access request is a request to read information stored at the virtual address, and wherein the processing unit is further configured to:
spawn a process to generate the information that is to be read in response to the memory access request;
write the generated information to the first physical page on the basis of the virtual address; and
read the generated information from the first physical page.

### Claim 14 (depends on 10)

The apparatus of claim 10, wherein the processing unit is further configured to allocate a plurality of physical pages including the first physical page to the free page pool.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the processing unit is further configured to:
remove the first physical page from the free page pool in response to mapping the first physical page to the virtual address.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the processing unit is further configured to:
determine a number of physical pages in the free page pool;
unmap at least one physical page from at least one corresponding virtual address in response to the number being less than a threshold; and
add the at least one unmapped physical page to the free page pool.

### Claim 17 (depends on 10)

The apparatus of claim 10, further comprising:
at least one cache that is configured to cache information stored in the second memory; and
at least one address translation buffer associated with the at least one cache, wherein receiving the memory access request comprises receiving the memory access request in response to the virtual address missing entries in the at least one address translation buffer.

### Claim 18 (depends on 10)

The apparatus of claim 10, further comprising:
a page table configured to store mappings of virtual addresses to physical addresses in the first memory and the second memory, wherein the processing unit is configured to modify the page table to indicate the mapping of the virtual address to the first physical page.

### Claim 19

An apparatus comprising:
a processing unit;
a first memory to store a dataset, wherein the first memory has a first latency to memory access requests from the processing unit; and
a second memory to store a sparse subset of the dataset, wherein the second memory has a second latency to memory access requests from the processing unit, and wherein the second latency is shorter than the first latency, and
wherein the processing unit is configured to:
receive a memory access request including a virtual address;
map a first physical page in a free page pool of the second memory to the virtual address in response to the virtual address not being mapped to a second physical page in the second memory; and
grant the memory access request to the second physical page that is mapped to the virtual address.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein the memory access request is a request to write to the virtual address, and wherein the processing unit is configured to initialize the first physical page to a known state.

### Claim 21 (depends on 20)

The apparatus of claim 20, wherein the processing unit is configured to write information to the first physical page on the basis of the virtual address.

### Claim 22 (depends on 19)

The apparatus of claim 19, wherein the memory access request is a request to read information stored at the virtual address, and wherein the processing unit is further configured to:
spawn a process to generate the information that is to be read in response to the memory access request;
write the generated information to the first physical page on the basis of the virtual address; and
read the generated information from the first physical page.