# US 2018/0024934 A1 · Scheduling independent and dependent operations for processing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0024934 A1 - Document ID: US20180024934A1 - Status: Published application - Kind: A1 - Application number: 15/213,981 - Filed: 2016-07-19 - Published: 2018-01-25 - Earliest claimed: 2016-07-19 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: Paul James Moyer; Richard Martin Born - Web page: https://patentgrep.com/patent/US20180024934A1 ## CPC - G06F 9/3814: {Implementation provisions of instruction buffers, e.g. prefetch buffer; banks} - G06F 12/0877: Cache access modes - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/3856: {Reordering of instructions, e.g. using queues or age tags} - G06F 2212/60: Details of cache memory - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A processor includes an operations scheduler to schedule execution of operations at, for example, a set of execution units or a cache of the processor. The operations scheduler periodically adds sets of operations to a tracking array, and further identifies when an operation in the tracked set is blocked from execution scheduling in response to, for example, identifying that the operation is dependent on another operation that has not completed execution. The processor further includes a counter that is adjusted each time an operation in the tracking array is blocked from execution, and is reset each time an operation in the tracking array is executed. When the value of the counter exceeds a threshold, the operations scheduler prioritizes the remaining tracked operations for execution scheduling. ## Claims ### Claim 1 A method, comprising: adding a first operation to a tracking array of a processor in response to the operation being received for scheduling for execution at the processor; adjusting a value of a counter by a first adjustment in response to blocking the first operation from being scheduled for execution while the first operation is stored at the tracking array; and in response to the value of the counter exceeding a threshold, suppressing scheduling of execution operations not stored the tracking array. ### Claim 2 (depends on 1) The method of claim 1, further comprising resetting the counter in response to the first operation being scheduled for execution while the first operation is stored at the tracking array. ### Claim 3 (depends on 1) The method of claim 1, wherein: the value of the counter is adjusted by a second adjustment in response to an operation stored at the tracking array being scheduled for execution. ### Claim 4 (depends on 1) The method of claim 1, wherein the first operation is blocked in response to identifying that the first operation is dependent on a second operation. ### Claim 5 (depends on 1) The method of claim 1, wherein the first operation is an operation awaiting scheduling for execution at an execution unit of a processor. ### Claim 6 (depends on 1) The method of claim 1, wherein the first operation is a memory access request awaiting scheduling for execution at a cache of the processor. ### Claim 7 (depends on 1) The method of claim 1, wherein the adding includes adding a plurality of operations ready for scheduling for execution at the processor to the tracking array, the plurality of operations including the first operation. ### Claim 8 A method, comprising: adding to a tracking array a plurality of operations ready for scheduling for execution at a processor; adjusting a counter in response to a first operation of the plurality of operations being blocked for scheduling for execution while the first operation is stored at the tracking array; and in response to the counter exceeding a threshold, prioritizing operations stored at the tracking array for execution at the processor. ### Claim 9 (depends on 8) The method of claim 8, further comprising removing the operation from the tracking array in response to the operation being scheduled for execution at the processor. ### Claim 10 (depends on 9) The method of claim 9, further comprising: resetting the counter in response to the operation being scheduled for execution at the processor. ### Claim 11 (depends on 9) The method of claim 9, wherein: the prioritizing comprises suppressing operations ready for scheduling and not stored at the tracking array from being scheduled for execution. ### Claim 12 (depends on 8) The method of claim 8, further comprising blocking the first operation from being scheduled for execution in response to identifying that the first operation is dependent on a second operation. ### Claim 13 (depends on 12) The method of claim 12, wherein the second operation is stored at the tracking array. ### Claim 14 A processor, comprising: an operations scheduler configured to schedule operations for execution at the processor; a tracking array configured to store a set of operations at the operations scheduler; a counter configured to adjust a value by a first adjustment in response to a first operation stored at the tracking array being blocked from being scheduled for execution at the operations scheduler; and wherein the operations scheduler is configured to, in response to the value of the counter exceeding a threshold, prioritize operations stored at the tracking array for execution. ### Claim 15 (depends on 14) The processor of claim 14, wherein the counter is configured to reset the value in response to the first operation being scheduled for execution while the first operation is stored at the tracking array. ### Claim 16 (depends on 14) The processor of claim 14, wherein the counter is configured to adjust the value of the counter by a second adjustment in response to an operation stored at the tracking array being scheduled for execution. ### Claim 17 (depends on 14) The processor of claim 14, wherein the operations scheduler is configured to block the first operation in response to identifying the first operation is dependent on a second operation. ### Claim 18 (depends on 14) The processor of claim 14, wherein the first operation is an operation awaiting scheduling for execution at an execution unit of the processor. ### Claim 19 (depends on 14) The processor of claim 14, wherein the first operation is a memory access request awaiting scheduling for execution at a cache of the processor. ### Claim 20 (depends on 14) The processor of claim 14, wherein the set of operations comprises a set of operations concurrently ready for scheduling at the operations scheduler.