# US 2018/0024926 A1 · Apparatuses and methods for transferring data

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- Number: US 2018/0024926 A1
- Document ID: US20180024926A1
- Status: Published application
- Kind: A1
- Application number: 15/214,982
- Filed: 2016-07-20
- Published: 2018-01-25
- Earliest claimed: 2016-07-20
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Daniel B. Penney; Gary L. Howe
- Web page: https://patentgrep.com/patent/US20180024926A1

## CPC

- G06F 12/0215: {with look ahead addressing means}
- G06F 12/0859: {with reload from main memory}
- G06F 13/16: for access to memory bus (G06F13/28 takes precedence)
- G06F 2212/1016: Performance improvement
- G06F 2212/1028: Power efficiency
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. The controller is configured to perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache, and perform a second operation concurrently with the first operation, the second operation beginning at a second address.

## Claims

### Claim 1

An apparatus, comprising:
a cache coupled to an array of memory cells; and
a controller configured to:
perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache; and
perform a second operation concurrently with the first operation, the second operation beginning at a second address.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first operation has a first transfer rate associated therewith and the second operation has a second transfer rate associated therewith.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the controller is configured to perform a third operation, the third operation comprising transferring data from the cache to a data bus.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the first address is a column address.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the first address of the cache is chosen based, at least in part, on a mode register setting.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the controller is further configured to select the first address of the array.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the controller is further configured to provide a command to the cache, and wherein the command includes the first address and a command to perform the first operation.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the first operation and the second operation each include at least one of a read operation or a write operation.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the controller is configured to provide a write commit command to an address adjacent to the first address.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the first address and the second address are not adjacent to one another.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the controller is further configured to perform the first operation at the first address concurrently with performing a third operation at a third address of the array of memory cells to transfer data to the cache.

### Claim 12

An apparatus, comprising:
an array of memory cells coupled to sensing circuitry including a sense amplifier and a compute component;
a cache coupled to the array of memory cells; and
a controller coupled to a plurality of registers and the array, wherein the controller is configured to:
transfer a first block of data from a first address of the array to a first address of the cache during a first time period;
transfer a second block of data from a second address of the array to a second address of the cache during a second time period; and
transfer a portion of the first block of data from the first address of the cache to a data bus during the second time period.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the controller comprises a bank processing control unit.

### Claim 14 (depends on 12)

The apparatus of claim 12, wherein the cache comprises at least one latch.

### Claim 15 (depends on 12)

The apparatus of claim 12, wherein the cache comprises an input/output (I/O) cache.

### Claim 16 (depends on 12)

The apparatus of claim 12, wherein the controller is further configured to transfer the portion of the first data from the cache to at least one DQ pin associated with the data bus.

### Claim 17 (depends on 12)

The apparatus of claim 12, wherein the data bus couples the array of memory cells together.

### Claim 18

An apparatus, comprising:
a host coupled to an interface;
a register communicatively coupled to the interface; and
a controller coupled to the host and the register, wherein the controller is configured to:
control writing data from the host to a cache; and
control writing the data from a first address of the cache to an array of memory cells while data is concurrently written from the host to a second address of the cache.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the controller is further configured to control writing data from the cache to an array of memory cells concurrently with writing the subsequent data to the cache.

### Claim 20 (depends on 18)

The apparatus of claim 18, wherein the register comprises a mode register.

### Claim 21 (depends on 18)

The apparatus of claim 18, wherein the controller is further configured to control writing data from the cache to an array of memory cells in response to the data being written to the cache.

### Claim 22

A method, comprising:
transferring data from an array of memory cells to a cache beginning at a first address; and
reading the data out of the cache in response to the data being transferred from the array of memory cells beginning at a second address.

### Claim 23 (depends on 22)

The method of claim 22, further comprising reading the data from the cache in response to completion of the data transferring from a first address of the array of memory cells to a first address of the cache.

### Claim 24 (depends on 22)

The method of claim 22, further comprising reading the data from the first address of the cache before all the data is transferred from the array of memory cells.

### Claim 25 (depends on 22)

The method of claim 22, further comprising receiving a starting column address information to identify a starting address associated with the array of memory cells, wherein the starting address of the array of memory cells is an address from which the data will start being transferred.

### Claim 26 (depends on 25)

The method of claim 25, further comprising latching the starting column address information to the cache with an external command.