# US 2018/0024877 A1 · Optimize data protection layouts based on distributed flash wear leveling > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0024877 A1 - Document ID: US20180024877A1 - Status: Published application - Kind: A1 - Application number: 15/592,069 - Filed: 2017-05-10 - Published: 2018-01-25 - Earliest claimed: 2016-07-22 - Assignees: Pure Storage, Inc. - Applicants: Pure Storage, Inc. - Inventors: Brian Gold; John Hayes; Robert Lee - Web page: https://patentgrep.com/patent/US20180024877A1 ## CPC - G06F 11/1044: {with specific ECC/EDC distribution} - G06F 3/0611: {in relation to response time} - G06F 3/0616: {in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]} - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 3/065: {Replication mechanisms} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 3/0688: {Non-volatile semiconductor memory arrays} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/3495: {Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically} - G06F 2212/7211: Wear leveling - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method for storing data in a storage system having solid-state memory is provided. The method includes determining portions of the solid-state memory that have a faster access rate and portions of the solid-state memory that have a slower access rate, relative to each other or to a threshold. The method includes writing data bits of erasure coded data to the portions of the solid-state memory having the faster access rate, and writing one or more parity bits of the erasure coded data to the portions of the solid-state memory having the slower access rate. A storage system is also provided. ## Claims ### Claim 1 A method for writing data to solid-state memory, performed by a storage system, the method comprising: determining that a first portion of solid-state memory of the storage system has a lower read latency than a second portion of the solid-state memory; writing a first portion of an error correction coded word to the first portion of the solid-state memory; and writing a second portion of the error correction coded word to the second portion of the solid-state memory. ### Claim 2 (depends on 1) The method of claim 1, wherein: the writing the first portion of the error correction coded word comprises writing data bits of the error correction coded word to the first portion of the solid-state memory; and the writing the second portion of the error correction coded word comprises writing parity bits of the error correction coded word to the second portion of the solid-state memory. ### Claim 3 (depends on 1) The method of claim 1, wherein the determining comprises: determining that the first portion of the solid-state memory has a lesser number of errors or a lower error rate than the second portion of the solid-state memory. ### Claim 4 (depends on 1) The method of claim 1, wherein the determining comprises: determining that the first portion of the solid-state memory has a lower age than the second portion of the solid-state memory. ### Claim 5 (depends on 1) The method of claim 1, wherein the determining comprises: determining that the first portion of the solid-state memory has a lower number of program and erase cycles than the second portion of the solid-state memory. ### Claim 6 (depends on 1) The method of claim 1, wherein the determining comprises: determining that the first portion of the solid-state memory has first and second pages of triple level cell flash memory and the second portion of the solid-state memory has third pages of the triple level cell flash memory. ### Claim 7 (depends on 1) The method of claim 1, wherein the writing the first portion and the second portion of the error correction coded word comprises: writing data bits of the error correction coded word to first solid-state drives having the first portion of the solid-state memory, in a storage array; and writing parity bits of the error correction coded word to second solid-state drives having the second portion of the solid-state memory, in the storage array. ### Claim 8 (depends on 1) The method of claim 1, wherein the writing the first portion and the second portion of the error correction coded word comprises: writing data bits of the error correction coded word to first solid-state storage units having the first portion of the solid-state memory, across storage nodes in a storage cluster; and writing parity bits of the error correction coded word to second solid-state storage units having the second portion of the solid-state memory, across the storage nodes in the storage cluster. ### Claim 9 A tangible, non-transitory, computer-readable media having instructions thereupon which, when executed by a processor, cause the processor to perform a method comprising: identifying a first portion of solid-state memory of a storage system that has a lower read latency than a second portion of the solid-state memory; writing a first portion of each of a plurality of error correction coded words to the first portion of the solid-state memory; and writing a second portion of each of the plurality of error correction coded words to the second portion of the solid-state memory. ### Claim 10 (depends on 9) The computer-readable media of claim 9, wherein: the writing the first portion of each of the plurality of error correction coded words comprises writing data bits of each of the plurality of error correction coded words to the first portion of the solid-state memory; and the writing the second portion of each of the plurality of error correction coded words comprises writing parity bits of each of the plurality of error correction coded words to the second portion of the solid-state memory. ### Claim 11 (depends on 9) The computer-readable media of claim 9, wherein the identifying comprises: identifying the first portion of the solid-state memory as having a lesser number of errors or a lower error rate than the second portion of the solid-state memory. ### Claim 12 (depends on 9) The computer-readable media of claim 9, wherein the identifying comprises: identifying the first portion of the solid-state memory as having a lower age than the second portion of the solid-state memory. ### Claim 13 (depends on 9) The computer-readable media of claim 9, wherein the identifying comprises: identifying the first portion of the solid-state memory as having a lower number of program and erase cycles than the second portion of the solid-state memory. ### Claim 14 (depends on 9) The computer-readable media of claim 9, wherein the identifying comprises: identifying the first portion of the solid-state memory as having first and second pages of triple level cell flash memory; and identifying the second portion of the solid-state memory as having third pages of the triple level cell flash memory. ### Claim 15 A storage system, comprising: solid-state memory; and one or more processors, configurable to: identify a first portion of the solid-state memory that has a lower read latency than a second portion of the solid-state memory; write a first portion of each of a plurality of error correction coded words to the first portion of the solid-state memory; and write a second portion of each of the plurality of error correction coded words to the second portion of the solid-state memory. ### Claim 16 (depends on 15) The storage system of claim 15, wherein: the solid-state memory and the one or more processors comprise a storage array having the one or more processors as a storage controller and the solid-state memory in a plurality of solid-state drives coupled to the storage controller; and the one or more processors configurable to write the first portion and the second portion of each of the plurality of error correction coded words comprises the storage controller configurable to write data bits of each of the plurality of error correction coded words to first solid-state drives having the first portion of the solid-state memory in the storage array and write parity bits of each of the plurality of error correction coded words to second solid-state drives having the second portion of the solid-state memory in the storage array. ### Claim 17 (depends on 15) The storage system of claim 15, wherein: the solid-state memory and the one or more processors comprise a storage cluster having a plurality of solid-state storage units each having at least one controller and a plurality of storage nodes each having at least one processor; and the one or more processors configurable to write the first portion and the second portion of each of the plurality of error correction coded words comprises the storage nodes configurable to write data bits of the plurality of error correction coded words to first solid-state storage units having the first portion of the solid-state memory, across storage nodes in the storage cluster and write parity bits of the plurality of error correction coded words to second solid-state storage units having the second portion of the solid-state memory, across the storage nodes in the storage cluster. ### Claim 18 (depends on 15) The storage system of claim 15, wherein the one or more processors configurable to identify comprises: the one or more processors configurable to identify the first portion of the solid-state memory as having a lesser number of errors or a lower error rate than the second portion of the solid-state memory. ### Claim 19 (depends on 15) The storage system of claim 15, wherein the one or more processors configurable to identify comprises: the one or more processors configurable to identify the first portion of the solid-state memory as having a lower number of program and erase cycles than the second portion of the solid-state memory. ### Claim 20 (depends on 15) The storage system of claim 15, wherein the one or more processors configurable to identify comprises: the one or more processors configurable to identify the first portion of the solid-state memory as having first and second pages of triple level cell flash memory and the second portion of the solid-state memory as having third pages of the triple level cell flash memory.