# US 2018/0024865 A1 · Parallel processing apparatus and node-to-node communication method

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- Number: US 2018/0024865 A1
- Document ID: US20180024865A1
- Status: Published application
- Kind: A1
- Application number: 15/614,169
- Filed: 2017-06-05
- Published: 2018-01-25
- Earliest claimed: 2016-07-22
- Assignees: Fujitsu Limited
- Applicants: Fujitsu Limited
- Inventors: Kazushige Saga
- Web page: https://patentgrep.com/patent/US20180024865A1

## CPC

- G06F 9/5072: {Grid computing}
- G06F 9/52: Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F 9/54: Interprogram communication
- H04L 67/10: in which an application is distributed across nodes in the network (software deployment G06F8/60; multiprogramming arrangements G06F9/46)
- G06F 16/172: Caching, prefetching or hoarding of files
- G06F 16/182: Distributed file systems
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A cross compiler generates a logical communication area number for first identifying information that is assigned to each of multiple processes contained in parallel processing. An area converter and an address acquisition unit keep correspondence information that makes it possible to, on the basis of the first identifying information and second identifying information representing the parallel processing, specify a memory area that is allocated according to each set of the second identifying information corresponding to the logical communication area number, receives a communication instruction containing the first identifying information, the second identifying information and the logical communication area number, and acquires a memory area corresponding to the acquired logical communication area number on the basis of the correspondence information. A communication controller performs communication by using the memory area that is acquired by the address acquisition unit.

## Claims

### Claim 1

A parallel processing apparatus comprising:
a generator that generates a logical communication area number for first identifying information that is assigned to each of multiple processes contained in parallel processing;
an acquisition unit that keeps correspondence information that makes it possible to, on the basis of the first identifying information and second identifying information representing the parallel processing, specify a memory area that is allocated according to each set of the second identifying information corresponding to the logical communication area number, receives a communication instruction containing the first identifying information, the second identifying information and the logical communication area number, and acquires a memory area corresponding to the acquired logical communication area number on the basis of the correspondence information; and
a communication unit that performs communication by using the memory area that is acquired by the acquisition unit.

### Claim 2 (depends on 1)

The parallel processing apparatus according to claim 1, further comprising:
a memory area determination unit that determines the memory areas to be allocated to the respective sets of the first identifying information when the parallel processing is executed; and
a correspondence information generator that generates the correspondence information by associating each of the memory areas to be allocated to respective sets of the first identifying information, which are determined by the memory area determination unit, with the logical communication area number.

### Claim 3 (depends on 1)

The parallel processing apparatus according to claim 1, wherein
the acquisition unit includes:
a specifying unit that keeps first correspondence information representing correspondence between the logical communication area number and a physical communication area number that is assigned to each set of the second identifying information and specifies, on the basis of the first correspondence information, the physical communication area number corresponding to the acquired logical communication area number; and
an extraction unit that keeps second correspondence information representing correspondence between the physical communication area number and the memory area and extracts the memory area on the basis of the physical communication area number that is specified by the specifying unit and the second correspondence information.

### Claim 4 (depends on 1)

The parallel processing apparatus according to claim 1, wherein the acquisition unit has, as the correspondence information, a correspondence table that makes it possible to specify the memory area corresponding to the logical communication area number on the basis of the first identifying information and the second identifying information.

### Claim 5

A node-to-node communication method comprising:
generating a logical communication area number for first identifying information that is assigned to each of multiple processes contained in parallel processing;
receiving a communication instruction containing the first identifying information, second identifying information representing the parallel processing, and the logical communication area number;
acquiring the first identifying information, the second identifying information, and the logical communication area number from the received communication instruction;
acquiring a memory area corresponding to the acquired logical communication area number by using correspondence information that makes it possible to, on the basis of the first identifying information and the second identifying information, specify a memory area that is allocated according to the second identifying information corresponding to the logical communication area number; and
performing communication by using the acquired memory area.