# US 2018/0024753 A1 · Internally preconditioning solid state drives for various workloads > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0024753 A1 - Document ID: US20180024753A1 - Status: Published application - Kind: A1 - Application number: 15/216,541 - Filed: 2016-07-21 - Published: 2018-01-25 - Earliest claimed: 2016-07-21 - Assignees: HGST Netherlands B.V. - Applicants: HGST Netherlands B.V. - Inventors: Timothy Glen Hallett; Anton John Neu; Phillip Peterson - Web page: https://patentgrep.com/patent/US20180024753A1 ## CPC - G06F 3/0613: {in relation to throughput} - G06F 3/0632: {by initialisation or re-initialisation of storage systems} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/06: Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/40: using compression techniques - G11C 29/44: Indication or identification of errors, e.g. for repair - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G06F 3/0685: {Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays} - G06F 12/0223: {User address space allocation, e.g. contiguous or non contiguous base addressing} - G06F 12/0623: {for memory modules} - G06F 12/0692: {Multiconfiguration, e.g. local and global addressing} - G06F 2212/1016: Performance improvement - G06F 2212/2022: Flash memory - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7206: Reconfiguration of flash memory system - G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices - G06F 2212/7211: Wear leveling - G11C 2029/4002: {Comparison of products, i.e. test results of chips or with golden chip} - G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Systems and methods for internally preconditioning SSDs for various workloads are disclosed. One such method involves (1) receiving preconditioning parameters including an invalidity distribution across ribbons, a transfer size of workloads, and a randomness of workloads, (2) generating workload data including a percentage of random data and a percentage of non-random data, where the percentages are based on the randomness of workloads parameter, (3) determining preselected physical block addresses (PBAs) of a ribbon using the invalidity distribution parameter, (4) writing a portion of the workload data to each of the preselected PBAs of the ribbon using a preselected transfer size until the ribbon is full, where the transfer size is based on the transfer size of workloads parameter, (5) marking all PBAs of the ribbon that were not preselected using the invalidity distribution parameter as being invalid, and (6) repeating (2) to (5) until a preselected end condition is met. ## Claims ### Claim 1 A method for internally preconditioning a solid state drive (SSD) comprising a non-volatile memory (NVM), the method comprising: (1) receiving a plurality of preselected preconditioning parameters comprising an invalidity distribution across ribbons, a transfer size of workloads, and a randomness of workloads; (2) generating workload data comprising a preselected percentage of random data and a preselected percentage of non-random data, wherein the preselected percentage of random data and the preselected percentage of non-random data are based on the randomness of workloads parameter; (3) determining a plurality of preselected physical block addresses (PBAs) of a ribbon of the NVM using the invalidity distribution across ribbons parameter; (4) writing a portion of the workload data to each of the preselected PBAs of the ribbon using a preselected transfer size until the ribbon is full, wherein the preselected transfer size is based on the transfer size of workloads parameter; (5) marking all PBAs of the ribbon that were not preselected using the invalidity distribution across ribbons parameter as being invalid; and (6) repeating (2) to (5) until a preselected end condition is met. ### Claim 2 (depends on 1) The method of claim 1, wherein the repeating (2) to (5) until the preselected end condition is met comprises repeating (2) to (5) until each ribbon in the NVM is full. ### Claim 3 (depends on 1) The method of claim 1: wherein the receiving the plurality of preselected preconditioning parameters comprises receiving, from a host at the SSD, the plurality of preselected precondition parameters; wherein the generating the workload data comprises generating, at the SSD, the workload data; wherein the determining the plurality of preselected PBAs comprises determining, at the SSD, the plurality of preselected PBAs; and wherein the writing a portion of the workload data to each of the preselected PBAs of the ribbon comprises writing, at the SSD, a portion of the workload data to each of the preselected PBAs of the ribbon. ### Claim 4 (depends on 1) The method of claim 1, further comprising: searching an indirection table of the SSD for holes; and writing random data from the workload data to each of the holes. ### Claim 5 (depends on 1) The method of claim 1, wherein the plurality of preselected preconditioning parameters further comprises an age of ribbons; the method further comprising: updating a ribbon erase count table of the SSD based on the age of ribbons parameter. ### Claim 6 (depends on 1) The method of claim 1, wherein the generating the workload data comprises generating the workload data using a pseudo random number generator. ### Claim 7 (depends on 1) The method of claim 1, wherein the transfer size of workloads parameter comprises at least one of 4 k blocks or 64 k blocks. ### Claim 8 (depends on 1) The method of claim 1, wherein the randomness of workloads parameter is a value between zero and one, inclusive. ### Claim 9 (depends on 1) The method of claim 1, further comprising: determining logical block addresses for each of the plurality of PBAs using either the random data of the workload data or the non-random data of the workload data; and wherein the writing the portion of the workload data to each of the preselected PBAs of the ribbon comprises writing one of the logical block addresses to each of the preselected PBAs of the ribbon. ### Claim 10 A system for internally preconditioning a solid state drive (SSD), the system comprising: a memory; a non-volatile memory (NVM); a processor coupled to the memory and the NVM and configured to: (1) receive a plurality of preselected precondition parameters comprising an invalidity distribution across ribbons, a transfer size of workloads, and a randomness of workloads; (2) generate workload data comprising a preselected percentage of random data and a preselected percentage of non-random data, wherein the preselected percentage of random data and the preselected percentage of non-random data are based on the randomness of workloads parameter; (3) determine a plurality of preselected physical block addresses (PBAs) of a ribbon of the NVM using the invalidity distribution across ribbons parameter; (4) write a portion of the workload data to each of the preselected PBAs of the ribbon using a preselected transfer size until the ribbon is full, wherein the preselected transfer size is based on the transfer size of workloads parameter; (5) mark all PBAs of the ribbon that were not preselected using the invalidity distribution across ribbons parameter as being invalid; and (6) repeat (2) to (5) until a preselected end condition is met. ### Claim 11 (depends on 10) The system of claim 10, wherein the processor is further configured to repeat (2) to (5) until each ribbon in the NVM is full. ### Claim 12 (depends on 10) The system of claim 10, wherein the processor is further configured to receive, from a host, the plurality of preselected precondition parameters. ### Claim 13 (depends on 10) The system of claim 10, wherein the processor is further configured to: search an indirection table of the SSD for holes; and write random data from the workload data to each of the holes. ### Claim 14 (depends on 10) The system of claim 10: wherein the plurality of preselected preconditioning parameters further comprises an age of ribbons; and wherein the processor is further configured to update a ribbon erase count table of the SSD based on the age of ribbons parameter. ### Claim 15 (depends on 10) The system of claim 10, wherein the processor is further configured to generate the workload data using a pseudo random number generator. ### Claim 16 (depends on 10) The system of claim 10, wherein the transfer size of workloads parameter comprises at least one of 4 k blocks or 64 k blocks. ### Claim 17 (depends on 10) The system of claim 10, wherein the randomness of workloads parameter is a value between zero and one, inclusive. ### Claim 18 (depends on 10) The system of claim 10, wherein the processor is further configured to: determine logical block addresses for each of the plurality of PBAs using either the random data of the workload data or the non-random data of the workload data; and write one of the logical block addresses to each of the preselected PBAs of the ribbon.