# US 2018/0024749 A1 · Information processing apparatus, non-transitory computer-readable recording medium having stored therein program, and method for processing information > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0024749 A1 - Document ID: US20180024749A1 - Status: Published application - Kind: A1 - Application number: 15/612,407 - Filed: 2017-06-02 - Published: 2018-01-25 - Earliest claimed: 2016-07-25 - Assignees: Fujitsu Limited - Applicants: Fujitsu Limited - Inventors: Hirokazu OHTA; NOBUAKI SASAKI; Kazunari YONEYA - Web page: https://patentgrep.com/patent/US20180024749A1 ## CPC - G06F 13/1663: {Access to shared memory} - G06F 11/3037: {where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00)} - G06F 11/3051: {Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs (verification or detection of system hardware configuration G06F11/2247)} - G06F 12/0684: {with feedback, e.g. presence or absence of unit detected by addressing, overflow detection} - G06F 2212/1024: Latency reduction - G06F 2212/2542: Non-uniform memory access [NUMA] architecture - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An information processing apparatus includes: a first calculator and a second calculator being coupled to each other via a bus, and each making a memory access, designating a logical address; a first memory being coupled to the first calculator; and a second memory being coupled to the second calculator and being accessed from the first calculator via the bus, wherein the first memory determines, based on a time from issue of a request for the memory access to response to the request, whether a memory having a physical address associated with the logical address is the first memory or the second memory. With this configuration, it is possible to specify whether a memory being accessed using a logical address is a local memory or a remote memory. ## Claims ### Claim 1 An information processing apparatus comprising: a first calculator and a second calculator being coupled to each other via a bus, and each making a memory access, designating a logical address; a first memory being coupled to the first calculator; and a second memory being coupled to the second calculator and being accessed from the first calculator via the bus, wherein the first memory determines, based on a time from issue of a request for the memory access to response to the request, whether a memory having a physical address associated with the logical address is the first memory or the second memory. ### Claim 2 (depends on 1) The information processing apparatus according to claim 1, wherein the first calculator: divides regions of the first memory and the second memory into unit blocks of a predetermined size; obtains access times taken for accesses to the unit blocks, the accesses being made, designating respective logical addresses associated one with each of the unit blocks; stores the logical addresses and the access times in a first table in association with each other; recognizes a logical address associated with a shorter access time than other access times, among the logical addresses stored in the first table, as a first logical address; and determines a memory having a first physical address associated with the first logical address to be the first memory. ### Claim 3 (depends on 1) The information processing apparatus according to claim 1, wherein the first calculator: divides regions of the first memory and the second memory into unit blocks of a predetermined size; obtains access times taken for accesses to the unit blocks, the accesses being made, designating respective logical addresses associated one with each of the unit blocks; obtains access speeds of the unit blocks based on the obtained access times and the predetermined size; stores the logical addresses and the access speeds in a first table in association with each other; recognizes a logical address associated with a faster access speed than other access speeds, among the logical addresses stored in the first table, as a first logical address; and determines a memory having a first physical address associated with the first logical address to be the first memory. ### Claim 4 (depends on 2) The information processing apparatus according to claim 2, wherein the first calculator: recognizes the other logical addresses as second logical addresses; and determines a memory having second physical addresses associated with the second logical addresses to be the second memory. ### Claim 5 (depends on 2) The information processing apparatus according to claim 2, wherein the predetermined size is set to be larger than a size of a cache memory for the first calculator. ### Claim 6 (depends on 4) The information processing apparatus according to claim 4, wherein the first calculator: generates a second table that specifies an association of the first logical address or the second logical address with the first memory or the second memory; and tests a path between the first calculator and the second calculator with reference to the second table. ### Claim 7 A non-transitory computer-readable recording medium having stored therein a program instructing a first calculator to execute a process comprising: in an information processing apparatus comprising the first calculator and a second calculator being coupled to each other via a bus, and each making a memory access, designating a logical address; a first memory being coupled to the first calculator; and a second memory being coupled to the second calculator and being accessed from the first calculator via the bus, determining based on a time from issue of a request for the memory access to response to the request, whether a memory having a physical address associated with the logical address is the first memory or the second memory. ### Claim 8 (depends on 7) The non-transitory computer-readable recording medium according to claim 7, wherein the process further comprises: dividing regions of the first memory and the second memory into unit blocks of a predetermined size; obtaining access times taken for accesses to the unit blocks, the accesses being made, designating respective logical addresses associated one with each of the unit blocks; storing the logical addresses and the access times in a first table in association with each other; recognizing a logical address associated with a shorter access time than other access times, among the logical addresses stored in the first table, as a first logical address; and determining a memory having a first physical address associated with the first logical address to be the first memory. ### Claim 9 (depends on 7) The non-transitory computer-readable recording medium according to claim 7, wherein the process further comprises: dividing regions of the first memory and the second memory into unit blocks of a predetermined size; obtaining access times taken for accesses to the unit blocks, the accesses being made, designating respective logical addresses associated one with each of the unit blocks; obtaining access speeds of the unit blocks based on the obtained access times and the predetermined size; storing the logical addresses and the access speeds in a first table in association with each other; recognizing a logical address associated with a faster access speed than other access speeds, among the logical addresses stored in the first table, as a first logical address; and determining a memory having a first physical address associated with the first logical address to be the first memory. ### Claim 10 (depends on 8) The non-transitory computer-readable recording medium according to claim 8, wherein the process further comprises: recognizing the other logical addresses as second logical addresses; and determining a memory having second physical addresses associated with the second logical addresses to be the second memory. ### Claim 11 (depends on 8) The non-transitory computer-readable recording medium according to claim 8, wherein the predetermined size is set to be larger than a size for a cache memory of the first calculator. ### Claim 12 (depends on 10) The non-transitory computer-readable recording medium according to claim 10, wherein the process further comprises: generating a second table that specifies an association of the first logical address or the second logical address with the first memory or the second memory; and testing a path between the first calculator and the second calculator with reference to the second table. ### Claim 13 A method for processing information comprising: at a first calculator included in an information processing apparatus comprising the first calculator and a second calculator being coupled to each other via a bus, and each making a memory access, designating a logical address; a first memory being coupled to the first calculator; and a second memory being coupled to the second calculator and being accessed from the first calculator via the bus, determining based on a time from issue of a request for the memory access to response to the request, whether a memory having a physical address associated with the logical address is the first memory or the second memory. ### Claim 14 (depends on 13) The method according to claim 13, further comprising: at the first calculator, dividing regions of the first memory and the second memory into unit blocks of a predetermined size; obtaining access times taken for accesses to the unit blocks, the accesses being made, designating respective logical addresses associated one with each of the unit blocks; storing the logical addresses and the access times in a first table in association with each other; recognizing a logical address associated with a shorter access time than other access times, among the logical addresses stored in the first table, as a first logical address; and determining a memory having a first physical address associated with the first logical address to be the first memory. ### Claim 15 (depends on 13) The method according to claim 13, further comprising: at the first calculator, dividing regions of the first memory and the second memory into unit blocks of a predetermined size; obtaining access times taken for accesses to the unit blocks, the accesses being made, designating respective logical addresses associated one with each of the unit blocks; obtaining access speeds of the unit blocks based on the obtained access times and the predetermined size; storing the logical addresses and the access speeds in a first table in association with each other; recognizing a logical address associated with a faster access speed than other access speeds, among the logical addresses stored in the first table, as a first logical address; and determining a memory having a first physical address associated with the first logical address to be the first memory. ### Claim 16 (depends on 14) The method according to claim 14, at the first calculator, recognizing the other logical addresses as second logical addresses; and determining a memory having second physical addresses associated with the second logical addresses to be the second memory. ### Claim 17 (depends on 14) The method according to claim 14, wherein the predetermined size is set to be larger than a size of a cache memory for the first calculator. ### Claim 18 (depends on 16) The method according to claim 16, further comprising: at the first calculator, generating a second table that specifies an association of the first logical address or the second logical address with the first memory or the second memory; and testing a path between the first calculator and the second calculator with reference to the second table.