# US 2018/0024618 A1 · Power Control in Integrated Circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0024618 A1 - Document ID: US20180024618A1 - Status: Published application - Kind: A1 - Application number: 15/652,737 - Filed: 2017-07-18 - Published: 2018-01-25 - Earliest claimed: 2016-07-20 - Assignees: Imec Vzw - Applicants: Imec Vzw - Inventors: Soeren Steudel; Liesbet Van der Perre; Bruno Mollekens - Web page: https://patentgrep.com/patent/US20180024618A1 ## CPC - G06F 1/3287: by switching off individual functional units in the computer system - G06F 1/3243: {Power saving in microcontroller unit} - G06F 1/3296: by lowering the supply or operating voltage - H03K 17/687: the devices being field-effect transistors - H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates - H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract An integrated circuit device comprising a power control unit for controlling the power of a power isle is disclosed. The power control unit comprises (i) a power gating switch implemented in the BEOL portion for switching ON/OFF the power to the power isle, (ii) a state recovery circuit comprising a memory element in the FEOL portion or BEOL portion and a transistor configuration in the BEOL portion, and (iii) a wake-up/sleep circuit in the BEOL portion adapted for receiving an identifier. The wake-up/sleep circuit is operatively connected with the power gating switch and with the state recovery circuit. Responsive to receiving the identifier, the wake-up/sleep circuit causes the power gating switch to switch OFF/ON the supply power to the power isle and causes the state recovery circuit to store/restore the state of the power isle. ## Claims ### Claim 1 An integrated circuit device comprising: a front-end-of-line portion; a back-end-of-line portion; and a power control unit for controlling a supply power of a power isle in the front-end-of-line portion, the power control unit comprising: a power gating switch implemented in the back-end-of-line portion, wherein the power gating switch is configured to switch ON or OFF the supply power to the power isle; a state recovery circuit configured to store and restore a state of the power isle, wherein the state recovery circuit comprises (i) at least one memory element implemented in the front-end-of-line portion or back-end-of-line portion and (ii) a transistor configuration in the back-end-of-line portion; and a wake-up/sleep circuit implemented in the back-end-of-line portion and configured to receive an identifier, wherein the wake-up/sleep circuit is operatively connected with the power gating switch and with the state recovery circuit, and wherein the wake-up/sleep circuit is configured to perform a wake-up/sleep process in response to receiving the identifier, the wake-up/sleep process comprising at least one of: (i) causing the power gating switch to switch OFF the supply power to the power isle and causing the state recovery circuit to store a state of the power isle, or (ii) causing the power gating switch to switch ON the supply power to the power isle and causing the state recovery circuit to restore the state of the power isle. ### Claim 2 (depends on 1) The integrated circuit device of claim 1, wherein the transistor configuration in the back-end-of-line portion is connected with the memory element such that the transistor configuration reduces current leakage through the memory element. ### Claim 3 (depends on 1) The integrated circuit device of claim 1, wherein the back-end-of-line portion comprises metallization layers and wherein the power gating switch comprises a thin-film transistor in between at least two of the metallization layers of the back-end-of-line portion. ### Claim 4 (depends on 1) The integrated circuit device of claim 1, wherein the back-end-of-line portion comprises at least three metallization layers, and wherein the power gating switch comprises a thin-film transistor implemented above the 3rd metallization layer of the back-end-of-line portion when starting to count the metallization layers from the front-end-of-line portion. ### Claim 5 (depends on 1) The integrated circuit device of claim 1, wherein the at least one memory element of the state recovery circuit comprises a flip-flop comprising front-end-of-line transistors in the power isle, and wherein the transistor configuration in the back-end-of-line portion comprises a thin-film transistor directly on top of the flip-flop. ### Claim 6 (depends on 1) The integrated circuit device of claim 1, wherein the back-end-of-line portion comprises metallization layers, and wherein the wake-up/sleep circuit is implemented in a 3rd or higher metallization layer of the back-end-of-line portion. ### Claim 7 (depends on 1) The integrated circuit device of claim 1, wherein the wake-up/sleep circuit comprises a plurality of thin-film transistors. ### Claim 8 (depends on 1) The integrated circuit device of claim 1, wherein the wake-up/sleep circuit comprises a bus interface for receiving the identifier. ### Claim 9 (depends on 1) The integrated circuit device of claim 1, further comprising a power management module and a plurality of the power control units, wherein the power management module is connected by a bus to each wake-up/sleep circuit of each power control unit of the plurality of the power control units, and wherein the power management module is configured to transmit the identifier over the bus to each wake-up/sleep circuit of each power control unit of the plurality of the power control units. ### Claim 10 (depends on 1) The integrated circuit device of claim 1, further comprising a plurality of the power control units, wherein the wake-up/sleep circuit of each power control unit of the plurality of the power control units is connected by a bus to one or more neighboring power control units of the plurality of the power control units. ### Claim 11 An integrated circuit device comprising: a front-end-of-line portion; a back-end-of-line portion; and a plurality of power control units for controlling supply power to a plurality of power isles in the front-end-of-line portion, each power control unit of the plurality of power control units comprising: a power gating switch implemented in the back-end-of-line portion, wherein the power gating switch is configured to switch ON or OFF the supply power to a respective power isle of the plurality of power isles; a state recovery circuit configured to store and restore a state of the respective power isle, wherein the state recovery circuit comprises (i) at least one memory element implemented in the front-end-of-line portion or back-end-of-line portion and (ii) a transistor configuration in the back-end-of-line portion; and a wake-up/sleep circuit implemented in the back-end-of-line portion and configured to receive an identifier, wherein the wake-up/sleep circuit is operatively connected with the power gating switch and with the state recovery circuit, and wherein the wake-up/sleep circuit is configured to perform a wake-up/sleep process in response to receiving the identifier, the wake-up/sleep process comprising at least one of: (i) causing the power gating switch to switch OFF the supply power to the respective power isle and causing the state recovery circuit to store a state of the respective power isle, or (ii) causing the power gating switch to switch ON the supply power to the respective power isle and causing the state recovery circuit to restore the state of the respective power isle. ### Claim 12 (depends on 11) The integrated circuit device of claim 11, wherein the transistor configuration in the back-end-of-line portion is connected with the memory element such that the transistor configuration reduces current leakage through the memory element. ### Claim 13 (depends on 11) The integrated circuit device of claim 11, wherein the back-end-of-line portion comprises metallization layers and wherein the power gating switch comprises a thin-film transistor in between at least two of the metallization layers of the back-end-of-line portion. ### Claim 14 (depends on 11) The integrated circuit device of claim 11, wherein the back-end-of-line portion comprises at least three metallization layers, and wherein the power gating switch comprises a thin-film transistor implemented above the 3rd metallization layer of the back-end-of-line portion when starting to count the metallization layers from the front-end-of-line portion. ### Claim 15 (depends on 11) The integrated circuit device of claim 11, wherein the at least one memory element of the state recovery circuit comprises a flip-flop comprising front-end-of-line transistors in the power isle, and wherein the transistor configuration in the back-end-of-line portion comprises a thin-film transistor directly on top of the flip-flop. ### Claim 16 (depends on 11) The integrated circuit device of claim 11, wherein the back-end-of-line portion comprises metallization layers, and wherein the wake-up/sleep circuit is implemented in a 3rd or higher metallization layer of the back-end-of-line portion. ### Claim 17 (depends on 11) The integrated circuit device of claim 11, wherein the wake-up/sleep circuit comprises a plurality of thin-film transistors. ### Claim 18 (depends on 11) The integrated circuit device of claim 11, wherein the wake-up/sleep circuit comprises a bus interface for receiving the identifier. ### Claim 19 (depends on 11) The integrated circuit device of claim 11, further comprising a power management module connected by a bus to the wake-up/sleep circuit of each power control unit of the plurality of the power control units, and wherein the power management module is configured to transmit the identifier over the bus to the wake-up/sleep circuit of each power control unit of the plurality of the power control units. ### Claim 20 (depends on 11) The integrated circuit device of claim 11, wherein the wake-up/sleep circuit of each power control unit of the plurality of the power control units is connected by a bus to one or more neighboring power control units of the plurality of the power control units, and wherein the wake-up/sleep circuit of each power control unit of the plurality of the power control units is configured to receive the identifier over the bus from the one or more neighboring power control units of the plurality of the power control units.