# US 2018/0024610 A1 · Apparatus and method for setting a clock speed/voltage of cache memory based on memory request information

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- Number: US 2018/0024610 A1
- Document ID: US20180024610A1
- Status: Published application
- Kind: A1
- Application number: 15/217,911
- Filed: 2016-07-22
- Published: 2018-01-25
- Earliest claimed: 2016-07-22
- Assignees: Futurewei Technologies, Inc.
- Applicants: Futurewei Technologies, Inc.
- Inventors: Chukwuchebem Orakwue
- Web page: https://patentgrep.com/patent/US20180024610A1

## CPC

- G06F 1/324: by lowering clock frequency
- G06F 1/3225: of memory devices
- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 1/3296: by lowering the supply or operating voltage
- G06F 12/0815: Cache consistency protocols
- G06F 12/0862: with prefetch
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 2212/602: Details relating to cache prefetching
- G06F 2212/621: Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An apparatus and method are provided for setting a clock speed/voltage of cache memory based on memory request information. In response to receiving a memory request, information is identified in connection with the memory request, utilizing hardware that is in electrical communication with cache memory. Based on the information, a clock speed and/or a voltage of at least a portion of the cache memory is set, utilizing the hardware that is in electrical communication with the cache memory.

## Claims

### Claim 1

A method, comprising:
receiving a memory request;
in response to receiving the memory request, identifying information in connection with the memory request, utilizing hardware that is in electrical communication with cache memory; and
based on the information, setting at least one of a clock speed or a voltage of at least a portion of the cache memory, utilizing the hardware that is in electrical communication with the cache memory.

### Claim 2 (depends on 1)

The method of claim 1, wherein the information is related to at least a portion of at least one processor that caused the memory request.

### Claim 3 (depends on 1)

The method of claim 1, wherein the information is related to at least one of a clock speed or a voltage of at least a portion of at least one processor that caused the memory request.

### Claim 4 (depends on 1)

The method of claim 1, wherein the information is related to a type of the memory request.

### Claim 5 (depends on 4)

The method of claim 4, wherein the type of the memory request includes at least one of a read type, a coherence type, a write type, a prefetch type, or a flush type.

### Claim 6 (depends on 1)

The method of claim 1, wherein the information is related to a status of data that is a subject of the memory request.

### Claim 7 (depends on 6)

The method of claim 6, wherein the status of the data includes at least one of a hit status, a miss status, or a hit-on-prior-miss status.

### Claim 8 (depends on 1)

The method of claim 1, wherein the information is related to an action of the cache memory that is caused by the memory request.

### Claim 9 (depends on 8)

The method of claim 8, wherein the action of the cache memory that is caused by the memory request includes at least one of a read action, a write action, a request to external memory, a flush action, or a null action.

### Claim 10 (depends on 1)

The method of claim 1, wherein the information is identified from a field of the memory request.

### Claim 11 (depends on 10)

The method of claim 10, wherein the field of the memory request includes a requestor identification field.

### Claim 12 (depends on 10)

The method of claim 10, wherein the field of the memory request includes a type field.

### Claim 13 (depends on 1)

The method of claim 1, wherein the at least one of the clock speed or the voltage is set to at least one of a clock speed or a voltage of at least a portion of at least one processor that exhibits a highest clock speed or voltage.

### Claim 14 (depends on 1)

The method of claim 1, wherein at least one of the clock speed or the voltage is set for a subset of the cache memory.

### Claim 15 (depends on 14)

The method of claim 14, wherein the subset of the cache memory includes at least one bank of the cache memory.

### Claim 16 (depends on 1)

The method of claim 1, wherein at least one of the clock speed or the voltage is set for an entirety of the cache memory.

### Claim 17 (depends on 1)

The method of claim 1, wherein both the clock speed and the voltage are set, based on the information.

### Claim 18 (depends on 1)

The method of claim 1, wherein the hardware is integrated with the cache memory.

### Claim 19

An apparatus, comprising:
circuitry configured to, in response to receiving a memory request, identify information in connection with the memory request; and
circuitry configured to set at least one of a clock speed or a voltage of at least a portion of cache memory, based on the information.

### Claim 20

A system, comprising:
cache memory for storing data; and
hardware in electrical communication with the cache memory, the hardware configured to:
in response to receiving a memory request, identify information in connection with the memory request, and
set at least one of a clock speed or a voltage of at least a portion of the cache memory, based on the information.