# US 2018/0024189 A1 · Implementing register array (ra) repair using lbist > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0024189 A1 - Document ID: US20180024189A1 - Status: Published application - Kind: A1 - Application number: 15/214,767 - Filed: 2016-07-20 - Published: 2018-01-25 - Earliest claimed: 2016-07-20 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Steven M. Douskey; Michael J. Hamilton; Amanda R. Kaufer; Phillip A. Senum - Web page: https://patentgrep.com/patent/US20180024189A1 ## CPC - G01R 31/3187: Built-in tests - G01R 31/31853: {Test of registers} - G11C 29/12: Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} - G11C 29/44: Indication or identification of errors, e.g. for repair - G11C 29/4401: {for self repair} - G11C 29/84: {with improved access time or stability} - G11C 29/32: Serial access; Scan testing - G11C 2029/3202: {Scan chain} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method and circuit for implementing register array repair using Logic Built In Self Test (LBIST), and a design structure on which the subject circuit resides are provided. Register array repair includes identifying and creating a list of any repairable Register Arrays (RAs) that effect an LBIST fail result. Next a repair solution is detected for each of the repairable Register Arrays (RAs) isolating a failing location for the detected repair solution for each array. ## Claims ### Claim 1 A circuit for implementing register array repair using Logic Built In Self Test (LBIST), said circuit comprising: a plurality of Register Arrays (RAs), each RA including a redundant element enabling a single repair; a list of any repairable Register Arrays (RAs) effecting an LBIST fail result being identified; and a repair solution being detected for each of the repairable Register Arrays (RAs) in the list for isolating a failing location for the detected repair solution for each array. ### Claim 2 (depends on 1) The circuit as recited in claim 1 wherein each of the plurality of Register Arrays (RAs) includes a selectable iterate on each array repair data segment, said selectable iterate including an enable latch in a scan path for each focus array to allow iterating through repair trials responsive to a trigger signal from LBIST. ### Claim 3 (depends on 1) The circuit as recited in claim 1 wherein said repair solution being detected for each of the repairable Register Arrays (RAs) for isolating a failing location for the detected repair solution for each array includes choosing a fail array, repairing a failing location, and running LBIST. ### Claim 4 (depends on 1) The circuit as recited in claim 1 wherein said list of any repairable Register Arrays (RAs) effecting LBIST fail result being identified includes performing a full repair on all select arrays responsive to an LBIST fail, and checking for an LBIST fail change. ### Claim 5 (depends on 4) The circuit as recited in claim 4 includes choosing a focus array responsive to an LBIST fail change and performing a full repair on the focus array, and checking for a second LBIST fail change. ### Claim 6 (depends on 5) The circuit as recited in claim 5 includes logging the focus array as failing with a first signature responsive to the second LBIST fail change and choosing a next focus array for processing. ### Claim 7 A design structure embodied in a non-transitory machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: a circuit tangibly embodied in the non-transitory machine readable used in a design process, said circuit for implementing register array repair using Logic Built In Self Test (LBIST), said circuit comprising: a plurality of Register Arrays (RAs), each RA including a redundant element enabling a single repair; a list of any repairable Register Arrays (RAs) effecting LBIST fail result being identified; and a repair solution being detected for each of the repairable Register Arrays (RAs) in the list for isolating a failing location for the detected repair solution for each array, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit. ### Claim 8 (depends on 7) The design structure of claim 7, wherein the design structure comprises a netlist, which describes said circuit. ### Claim 9 (depends on 7) The design structure of claim 7, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits. ### Claim 10 (depends on 7) The design structure of claim 7, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications. ### Claim 11 (depends on 7) The design structure of claim 7, wherein each of the plurality of Register Arrays (RAs) includes a selectable iterate on each array repair data segment, said selectable iterate including an enable latch in a scan path for each focus array to allow iterating through repair trials responsive to a trigger signal from LBIST. ### Claim 12 (depends on 11) The design structure of claim 11, wherein said repair solution being detected for each of the repairable Register Arrays (RAs) for isolating a failing location for the detected repair solution for each array includes choosing a fail array, repairing a failing location, and running LBIST. ### Claim 13 (depends on 7) The design structure of claim 7, wherein said list of any repairable Register Arrays (RAs) effecting LBIST fail result being identified includes performing a full repair on all select arrays responsive to an LBIST fail, and checking for an LBIST fail change. ### Claim 14 (depends on 13) The design structure of claim 13, includes choosing a focus array responsive to an LBIST fail change and performing a full repair on the focus array, and checking for a second LBIST fail change. ### Claim 15 (depends on 14) The design structure of claim 14, includes logging the focus array as failing with a first signature responsive to the second LBIST fail change and choosing a next focus array for processing. ### Claim 16 A method for implementing register array repair using Logic Built In Self Test (LBIST), said method comprising: providing a plurality of Register Arrays (RAs), each RA including a redundant element enabling a single repair; identifying and creating a list of any repairable Register Arrays (RAs) that effect LBIST fail result; detecting a repair solution for each identified repairable Register Arrays (RAs) in the list, and isolating of a failing location for the detected repair solution for each array. ### Claim 17 (depends on 16) The method as recited in claim 16 includes providing each of the plurality of Register Arrays (RAs) with a selectable iterate on each array repair data segment, said selectable iterate including an enable latch in a scan path for each focus array to allow iterating through repair trials responsive to a trigger signal from LBIST. ### Claim 18 (depends on 16) The method as recited in claim 16 wherein detecting a repair solution for each identified repairable Register Arrays (RAs) in the list, and isolating of a failing location for the detected repair solution for each array includes choosing a fail array, repairing a failing location, and running LBIST. ### Claim 19 (depends on 16) The method as recited in claim 16 wherein identifying and creating a list of any repairable Register Arrays (RAs) that effect LBIST fail result includes performing a full repair on all select arrays responsive to an LBIST fail, and checking for a LBIST fail change, choosing a focus array responsive to the LBIST fail change and performing a full repair on the focus array, and checking for a second LBIST fail change. ### Claim 20 (depends on 19) The method as recited in claim 19 includes logging the focus array as failing with a first signature responsive to the second LBIST fail change and choosing a next focus array for processing.