Video processing system with multiple syntax parsing circuits and/or multiple post decoding circuits

A video processing system comprising:

• a storage device, comprising:
• a first buffer;
• and
• a second buffer;
• a demultiplexing circuit, arranged to receive an input bitstream, and perform a demultiplexing operation upon the input bitstream to write a video bitstream into the first buffer;
• a syntax parser, arranged to perform syntax parsing upon a plurality of bitstream segments of the video bitstream to generate a plurality of universal binary entropy (UBE) syntax data segments, respectively, and write the UBE syntax data segments into the second buffer, wherein each of the bitstream segments contains arithmetic-encoded syntax data, and each of the UBE syntax data segments contains no arithmetic-encoded syntax data;
• and
• a post decoder, comprising:
• a plurality of post decoding circuits, each comprising an UBE syntax decoder arranged to perform UBE syntax decoding upon one UBE syntax data segment read from the second buffer to output decoded syntax data;
• and
• a post decoding control circuit, arranged to assign a first UBE start point to a first post decoding circuit that is an idle post decoding circuit selected from the post decoding circuits, and trigger the selected first post decoding circuit to start post decoding of a first UBE syntax data segment that is read from the second buffer according to the first UBE start point, wherein the first UBE start point is indicative of a start address of the first UBE syntax data segment stored in the second buffer.