Electronic Appliance and Network of the Same

A network of electronic appliances comprising:

• a plurality of network units of electronic appliances comprising a first network unit and a plurality of second network units, wherein the first network unit is connected to at least one of the plurality of second network units in a topology;
• wherein each of the plurality of network units comprises a stem server and a plurality of peripheral devices connected to the stem server;
• wherein, in the first network unit, the stem server comprises at least one passcode and at least one list of a plurality of registration codes, wherein each list is associated to a respective one of the at least one passcode, wherein each of the plurality of registration codes of one list associating to one passcode corresponds to a respective one of the plurality of peripheral devices connecting to the stem server;
• wherein, in the first network unit, each of the plurality of registration codes is generated in response to a respective one of the at least one passcode using physical randomness of a respective one of the plurality of peripheral devices in correspondence to the passcode, wherein the plurality of registration codes is stored in the stem server in advance in correspondence to the passcode;
• wherein, in the first network unit, each of the plurality of peripheral devices comprises a plurality of components, wherein at least one of the plurality of components is a chip including at least one chip identification device, wherein the chip identification devices of the plurality of peripheral devices are different from each other;
• wherein, in the first network unit, the chip identification device sends a different output signal to the stem server, wherein the output signal is generated using physical randomness of the chip identification device according to the respective one of the at least one passcode received from the stem server;
• wherein, in the first network unit, the stem server compares the output signal with the list of the plurality of registration codes, and then determines the validity of the peripheral device;
• wherein, in the first network unit, the chip identification device comprises a plurality of identification cells;
• wherein, in the first network unit, the plurality of identification cells is semiconductor device cells which are made simultaneously in a same manufacturing process with the at least one chip;
• wherein, in the first network unit, each of the at least one chip comprises at least one module area;
• wherein, in the first network unit, the plurality of identification cells is distributed in one or more of the at least one module area;
• wherein, in the first network unit, an address of each of the plurality of identification cells is defined by a word line group including a plurality of word lines and a bit ling group including a plurality of bit lines, wherein the word line group and the bit ling group form the one or more of the at least one module area;
• wherein, in the first network unit, each of the plurality of identification cells electrically outputs at least a first value and a second value in response to a predetermined electrical input, and comprises at least two terminals;
• wherein, in the first network unit, if an electric current flowing between the at least two terminals with regard to a read voltage of the predetermined electrical input has a higher value than a value of a first threshold current, then the first value is regarded as being output, or if the electric current has a lower value than a value of a second threshold current, then the second value is regarded as being output;
• wherein, in the first network unit, the value of the first threshold current is higher than the value of the second threshold current;
• wherein, in the first network unit, if the electric current has a value higher than the value of the second threshold current and lower than the value of the first threshold current, then a third value is regarded as being output;
• and
• wherein, in the first network unit, the address of each of the plurality of identification cells outputting the third value is stored in a part of an inner memory of the peripheral device,
• wherein, in the first network unit, the address of each of the plurality of identification cells is defined by a row number allocated to one of the plurality of word lines and the plurality of bit lines, as well as a column number allocated to another of the plurality of word lines and the plurality of bit lines,
• wherein, if a plurality of row numbers includes irreversible errors in some of the plurality of identification cells, the plurality of row numbers generates physically unclonable chip identification of the peripheral node, wherein, in the first network unit, the physically unclonable chip identification is converted according to a predetermined format and is regarded as a physical address intrinsic to the peripheral node.