Method of improving clock recovery and related device

A method for a Mobile Industry Processor Interface (MIPI) slave device for improving clock recovery, the method comprising:

• receiving a wire state and generating three differential output signals, wherein the wire state is a combination of signal levels on three transmission wires;
• generating each of a first number of symbols based on a transition from a previous wire state to a present wire state which are obtained by using a clock signal generated by a clock recovery circuit of the MIPI slave device, wherein the pulse width of the clock signal is controlled by a timing delay configured in the clock recovery circuit;
• for each of the first number of symbols, determining whether each symbol is identical with a corresponding symbol of a reference symbol sequence and generating a determination result, wherein the reference symbol sequence comprises a plurality of consecutive symbols which comprise at least one of a first symbol value and a second symbol value, and wherein the first symbol value and the second symbol value bring relatively larger encoding jitters than other symbol values;
• and
• configuring, according to the first number of determination results, the value of the timing delay to control the pulse width of the clock signal.

A Mobile Industry Processor Interface (MIPI) slave device, comprising:

• a plurality of receivers, for receiving a wire state and generating three differential output signals, wherein the wire state is a combination of signal levels on three transmission wires;
• a symbol decoder, for generating each of a first number of symbols based on a transition from a previous wire state to a present wire state which are obtained by using a clock signal generated by a clock recovery circuit of the MIPI slave device, wherein the pulse width of the clock signal is controlled by a timing delay configured in the clock recovery circuit;
• and
• a determination unit, for determining whether each of the first number of symbols is identical with a corresponding symbol of a reference symbol sequence and generating a determination result, and configuring the value of the timing delay to control the pulse width of the clock signal according to the first number of determination results;
• wherein the reference symbol sequence comprises a plurality of consecutive symbols which comprise at least one of a first symbol value and a second symbol value, wherein the first symbol value and the second symbol value bring relatively larger encoding jitters than other symbol values.