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US 2018/0019767 A1Published application
Error correction and decoding
AssigneeQUALCOMM Incorporated
InventorsSeong-Ook JUNG, Sara CHOI, Byung Kyu SONG, JR., Taehui NA, Jisu KIM, Jung Pill KIM, Sungryul KIM, Taehyun KIM, Seung Hyuk KANG
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Abstract
Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.
Claims22
An error detection and correction apparatus, comprising:
- a syndrome generator configured to receive input data and to output a syndrome that indicates whether the input data includes an error;
- a positive edge triggered flip-flop that is configured to receive syndrome input based on the syndrome from the syndrome generator and to provide a syndrome output;
- and
- an error location decoder configured to receive the syndrome output from the positive edge triggered flip-flop.
1 more element
An error detection and correction apparatus, comprising:
- means for outputting a syndrome that indicates whether input data includes an error;
- a positive edge triggered flip-flop that is configured to receive syndrome input based on the syndrome from the syndrome generator and to provide a syndrome output;
- and
- means for generating an error location decoder output based on the syndrome output from the positive edge triggered flip-flop.
1 more element
Dependencies are inferred from the claim text.