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US 2018/0019756 A1Published application
Fractional-n phase locked loop delta sigma modulator noise reduction using charge pump interpolation
AssigneeQUALCOMM Incorporated
InventorsJingcheng ZHUANG, Xinhua CHEN, Frederic BOSSU, Yiwu TANG
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Abstract
A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the first output and the delayed output of the frequency divider.
Claims25
A phase locked loop, comprising:
- a frequency divider included in a feedback path, the frequency divider generating a first frequency divider output and a delayed frequency divider output that is a delayed version of the first frequency divider output;
- a charge pump to generate an output current based at least in part on the first frequency divider output and the delayed frequency divider output of the frequency divider;
- and
- at least one phase frequency detector (PFD) coupled between the frequency divider and the charge pump, the at least one PFD generating multiple down control signals.
1 more element
(canceled)
A method of reducing noise in a phase locked loop comprising:
- generating, by a frequency divider included in a feedback path, a first frequency divider output and a delayed frequency divider output that is a delayed version of the first frequency divider output;
- generating, by a charge pump, an output current based at least in part on the first frequency divider output and the delayed frequency divider output of the frequency divider;
- and
- generating multiple control signals based at least in part on the first frequency divider output and the delayed frequency divider output, the multiple control signals used to generate the output current, the multiple control signals comprising at least two down control signals.
1 more element
A phase locked loop comprising:
- means for generating a first frequency divider output and a delayed frequency divider output that is a delayed version of the first frequency divider output;
- means for generating an output current based at least in part on the first frequency divider output and the delayed frequency divider output;
- and
- means for generating multiple control signals based at least in part on the first frequency divider output and the delayed frequency divider output, the multiple control signals used to generate the output current, the multiple control signals comprising at least two down control signals.
1 more element
(canceled)
Dependencies are inferred from the claim text.