Cross-Coupled, Narrow Pulse, High Voltage Level Shifting Circuit With Voltage Domain Common Mode Rejection

A circuit, comprising:

• a high side circuit, including:
• current mirrors configured to generate mirrored currents that mirror a set signal and a reset signal that are generated in response to a set pulse and a reset pulse;
• a cross coupled current mode cancellation circuit connected to the current mirrors, wherein the cross coupled current mode cancellation circuit is configured to attenuate at least a portion of a slew current from a first one of the mirrored currents to generate an adjusted first signal, and to generate a first voltage at a resistor according to the adjusted first signal;
• and
• a high side driver configured to provide a high output signal according to activation to the first voltage.

A gate driver circuit, comprising:

• a first current mirror including:
• a first reference current transistor having a source connected to a positive reference voltage port;
• a first mirror transistor having a source connected to the positive reference voltage port and a gate connected to a gate and a drain of the first reference current transistor;
• and
• a second mirror transistor having a source connected to the positive reference voltage port and a gate connected to the gate and the drain of the first reference current transistor;
• a signaling set transistor connected in series between the drain of the first reference current transistor and a ground;
• and
• a cross coupled current mode cancellation circuit including:
• a first differential signal detection mirror transistor;
• a first resistor connected in series with the drain of the second mirror transistor and a negative reference voltage port;
• and
• a first common mode cancellation mirror transistor connected in parallel to the first resistor and in series between the drain of the second mirror transistor and the negative reference voltage port, and having a gate connected to a gate and a drain of a second differential signal detection mirror transistor.

A method, comprising:

• generating a set pulse in response to a received high input signal;
• generating a set signal in response to the set pulse;
• generating a first mirrored current that mirrors a current of the set signal;
• subtracting a second mirrored current from the first mirrored current to generate an adjusted first signal;
• generating a first voltage according to the adjusted first signal;
• and
• activating a high side driver according to the first voltage, the activating the high side driver causing the high side driver to provide a high output signal.