Semiconductor device

A semiconductor device comprising:

• a plurality of memory cells disposed in the form of an array and respectively comprised of FinFETs;
• a memory array having a plurality of data line pairs extending along respective columns of the array and coupled to the memory cells disposed in the columns of the array, and a plurality of word lines which extend along respective rows of the array and which are disposed in the rows of the array and coupled to the memory cells;
• and
• a driver circuit which is coupled to the word lines and which supplies a predetermined potential to the word line to be selected and supplies a ground potential to the word line to be non-selected,
• wherein the driver circuit includes:
• a plurality of unit driver circuits respectively coupled to the word lines;
• a first power supply wiring supplied with a first ground potential;
• a second power supply wiring supplied with a second ground potential having a potential lower than the first ground potential;
• and
• a ground potential setting circuit which is coupled to the unit driver circuits, the first power supply wiring, and the second power supply wiring and which selects the first ground potential or the second ground potential and supplies the same to the unit driver circuits as the ground potential,
• wherein each of the unit driver circuits includes a gate electrode, a first electrode coupled to the corresponding word line, and a second electrode supplied with the first ground potential or the second ground potential selected by the ground potential setting circuit.

A semiconductor device comprising:

• a memory cell having a pair of inverter circuits coupled to cross each other and each operated with a predetermined potential and a first ground potential as operating potentials, and transfer FinFETs each coupled between an output of the pair of inverter circuits and a data line and switch-controlled by a voltage at a word line;
• a first FinFET having a gate electrode, a first electrode coupled to the word line, and a second electrode supplied with a predetermined potential;
• and
• a second FinFET having a gate electrode, a first electrode coupled to the word line, and a second electrode supplied with a second ground potential lower than the first ground potential,
• wherein when the memory cell is selected, the predetermined potential is supplied to the word line through the first FinFET, and when the memory cell is non-selected, the second ground potential is supplied to the word line through the second FinFET.