Apparatus for design for testability of multiport register arrays

A method comprising:

• operating a first flip-flop latch array, the first flip-flop latch array including:
• a first set of master latches;
• a first set of slave latches coupled to the first set of master latches;
• and
• a first address port configured to select a subset of the first set of slave latches to function with the first set of master latches;
• operating a second flip-flop latch array, the second flip-flop latch array including:
• a second set of master latches;
• a second set of slave latches coupled to the second set of master latches;
• and
• a second address port configured to select a subset of the second set of slave latches to function with the second set of master latches, the second address port being different than the first address port;
• and
• operating an address counter, the address counter coupled to the first flip-flop latch array and the second flip-flop latch array, the address counter shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.

A register array comprising:

• means for operating a first flip-flop latch array, the first flip-flop latch array including:
• a first set of master latches;
• a first set of slave latches coupled to the first set of master latches;
• and
• a first address port configured to select a subset of the first set of slave latches to function with the first set of master latches;
• means for operating a second flip-flop latch array, the second flip-flop latch array including:
• a second set of master latches;
• a second set of slave latches coupled to the second set of master latches;
• and
• a second address port configured to select a subset of the second set of slave latches to function with the second set of master latches, the second address port being different than the first address port;
• and
• means for operating an address counter, the address counter coupled to the first flip-flop latch array and the second flip-flop latch array, the address counter shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.