Multi-level clock gate controls to address scan mode power droop and voltage bump requirement

An apparatus for multi-level clock gate control for testing electronic devices, comprising:

• a chain of at least two uncompressed flip-flops in an uncompressed chain of flip-flops;
• at least one flip-flop in communication with an OR gate, in communication with the chain of at least two uncompressed flip-flops in an uncompressed chain of flip-flops;
• a decompressor in communication with the chain of at least two uncompressed flip-flops in an uncompressed chain of flip-flops and the at least one flip-flop in communication with an OR gate;
• and
• a compressor in communication with the decompressor and the chain of at least two uncompressed flip-flops and the at least one flip-flop in communication with an OR gate.

An apparatus for multi-level clock gate control for testing electronic devices, comprising:

• means for identifying a number of clock gate levels from root level to last leaf level;
• means for ranking the clock gate levels from the root level to the last leaf level;
• means for determining a number of test enable commands for at least one test block of an electronic device;
• means for selectively connecting and disconnecting the test enable commands based on the ranked clock gate levels;
• and
• means for testing the at least one electronic device.

A non-transitory computer-readable medium containing instructions, which when performed by a processor, cause the processor to perform the following steps:

• identify a number of clock gate levels from root level to last leaf level;
• rank the clock gate levels from the root level to the last leaf level;
• determine a number of test enable commands for at least one test block of an electronic device;
• selectively connect and disconnect the test enable commands based on the ranked clock gate levels;
• and
• test the at least one test block of the electronic device.