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US 2018/0019706 A1Published application
Integrated circuit comprising fractional clock multiplication circuitry
AssigneeRambus Inc.
InventorsMasum Hossain, Farshid Aryanfar, Mohammad Hekmat, Reza Navid
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Abstract
Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
Claims21
1-20. (canceled)
An integrated circuit, comprising:
- a master clock generator comprising a ring oscillator, wherein the master clock generator outputs a first clock signal, and wherein an adjustment is made to a loop delay of the ring oscillator to maintain a substantially constant frequency multiplication ratio between the first clock signal and a reference clock signal;
- and
- a set of fractional clock multipliers, wherein each fractional clock multiplier comprises an injection-locked oscillator (ILO), wherein an adjustment is made to a loop delay of each ILO based on the adjustment that is made to the loop delay of the ring oscillator, and wherein each ILO generates a second clock signal based on the first clock signal.
A method, comprising:
- generating a first clock signal by using a master clock generator, wherein the master clock generator comprises a ring oscillator;
- making adjustments to a loop delay of the ring oscillator to maintain a substantially constant frequency multiplication ratio between the first clock signal and a reference clock signal;
- generating a second clock signal by using a fractional clock multiplier, wherein the fractional clock multiplier generates the second clock signal based on the first clock signal by using an injection-locked oscillator (ILO);
- and
- making adjustments to a loop delay of the ILO based on the adjustment that is made to the loop delay of the ring oscillator.
2 more elements
An integrated circuit, comprising:
- a first clock domain comprising circuitry that is clocked by a first clock signal;
- a master clock generator comprising a ring oscillator, wherein the master clock generator outputs the first clock signal, and wherein an adjustment is made to a loop delay of the ring oscillator to maintain a substantially constant frequency multiplication ratio between the first clock signal and a reference clock signal;
- a fractional clock multiplier comprising an injection-locked oscillator (ILO), wherein an adjustment is made to a loop delay of the ILO based on the adjustment that is made to the loop delay of the ring oscillator, and wherein the ILO generates a second clock signal based on the first clock signal;
- and
- a second clock domain comprising circuitry that is clocked by the second clock signal.
2 more elements
Dependencies are inferred from the claim text.