Programmable bulk finfet antifuses
AssigneeInternational Business Machines Corporation
InventorsPraneet Adusumilli, Alexander Reznicek, Oscar van der Straten
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Abstract
An antifuse device includes a gate structure formed on a substrate including first spacers formed in an upper portion and a conductive material formed in a lower portion below the first spacers. Two conductive regions are disposed adjacent to the gate structure and on opposite sides of the gate structure. A dielectric barrier is formed between the conductive material and each of the conductive regions such that a dual antifuse is formed across the dielectric barrier between the conductive material and the conductive regions on each side of the gate structure.
Claims20
An antifuse device, comprising:
- a gate structure formed on a substrate including first spacers formed in an upper portion thereof and a conductive material formed in a lower portion thereof below the first spacers;
- two conductive regions disposed adjacent to the gate structure and on opposite sides of the gate structure;
- and
- a dielectric barrier formed between the conductive material and each of the conductive regions such that a dual antifuse is formed across the dielectric barrier between the conductive material and the conductive regions on each side of the gate structure.
An antifuse device, comprising:
- a substrate;
- a punch through stopper layer formed by doping the substrate;
- a gate structure formed over the punch through stopper layer including first spacers formed in an upper portion and a conductive material formed in a lower portion below the first spacers, the conductive material extending below the first spacers to form a first antifuse electrode;
- two conductive regions disposed adjacent to the gate structure and on opposite sides of the gate structure, the two conductive regions each forming a second antifuse electrode;
- and
- a dielectric barrier formed between the first antifuse electrode and the second antifuse electrodes such that a dual antifuse is formed across the dielectric barrier between the conductive material and the conductive regions on each side of the gate structure.
A method for forming an antifuse device using complementary metal oxide semiconductor (CMOS) processing, comprising:
- forming a gate structure on a substrate including first spacers formed in an upper portion of the gate structure, a dielectric barrier formed in a lower portion of the gate structure and a conductive material formed in the lower portion of the gate structure below the first spacers;
- and
- forming two conductive regions disposed adjacent to the gate structure and on opposite sides of the gate structure such that a dual antifuse is formed across the dielectric barrier between the conductive material and the conductive regions on each side of the gate structure.
Dependencies are inferred from the claim text.