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US 2018/0019320 A1Published application
Inp-based transistor fabrication
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., Purdue Research Foundation
InventorsPeide Ye, Zhiyuan Cheng, Yi Xuan, Yanqing Wu, Bunmi Adekore, James Fiorenza
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Abstract
Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device are disclosed. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.
Claims20
A method comprising:
- forming a mask layer over a substrate, the substrate comprising a first crystalline semiconductor material having a first lattice constant, the mask layer comprising a non-crystalline dielectric material;
- patterning the mask layer to form an opening in the mask layer, the opening exposing a portion of the substrate;
- forming a buffer layer in the opening, the buffer layer comprising a second crystalline semiconductor material having a second lattice constant, the second lattice constant being different from the first lattice constant, a topmost surface of the buffer layer being below a topmost surface of the mask layer, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening;
- forming a semiconductor layer over the buffer layer in the opening, the semiconductor layer comprising a third crystalline semiconductor material having a third lattice constant, the third lattice constant being substantially same as the second lattice constant;
- and
- forming a gate stack over the semiconductor layer.
3 more elements
A method comprising:
- forming a mask layer over a substrate, the substrate comprising a first crystalline semiconductor material having a first lattice constant, the mask layer comprising a non-crystalline dielectric material;
- patterning the mask layer to form an opening in the mask layer, the opening exposing a surface of the substrate;
- epitaxially growing a semiconductor layer over the mask layer and in the opening, the semiconductor layer comprising a second crystalline semiconductor material having a second lattice constant, the second lattice constant being different from the first lattice constant, dislocation defects within the semiconductor layer extending laterally and terminating at a sidewall of the opening;
- and
- forming a gate stack over the semiconductor layer.
2 more elements
A method comprising:
- forming a non-crystalline dielectric layer over a substrate, the substrate comprising a first crystalline semiconductor material having a first lattice constant;
- etching the non-crystalline dielectric layer to form an opening in the non-crystalline dielectric layer, the opening exposing a portion of the substrate, the opening having a first width and a first height;
- epitaxially growing a buffer layer in the opening, the buffer layer comprising a second crystalline semiconductor material having a second lattice constant, the second lattice constant being different from the first lattice constant, the buffer layer having a second height less than the first height, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening below a third height, the third height being less than the second height, the third height being between one half of the first width and two times the first width;
- epitaxially growing a semiconductor layer over the buffer layer in the opening, the semiconductor layer comprising a third crystalline semiconductor material having a third lattice constant, the third lattice constant being substantially same as the second lattice constant;
- forming a gate dielectric over the semiconductor layer;
- and
- forming a gate electrode over the gate dielectric.
4 more elements
Dependencies are inferred from the claim text.