Methods of manufacturing image sensors

A method of manufacturing an image sensor, the method comprising:

• forming a plurality of photodiodes in a semiconductor layer in an active pixel region and a peripheral region;
• forming a structure including a plurality of insulating interlayers and a plurality of wiring structures on a first surface of the semiconductor layer in the active pixel region, the peripheral region and an input/output (I/O) region;
• partially etching the semiconductor layer to form an isolation trench therethrough, the isolation trench exposing a first insulating interlayer of the plurality of insulating interlayers;
• forming an insulation layer on a second surface of the semiconductor layer and an inner wall of the isolation trench, the second surface being opposite the first surface;
• partially etching the semiconductor layer and the first insulating interlayer in the I/O region to form a via hole therethrough, the via hole exposing a first wiring structure of the plurality of wiring structures;
• sequentially forming a first metal layer and a second metal layer on the insulation layer and the via hole;
• patterning the second metal layer to form a second pad pattern on the semiconductor layer in the I/O region, so that the first metal layer is exposed in the active pixel region and the peripheral region;
• forming an anti-reflective layer on the first metal layer and the second pad pattern;
• and
• patterning the anti-reflective layer and the first metal layer to form a light blocking structure including the first metal layer and the anti-reflective layer in the peripheral region and a pad structure including a via contact, a first pad pattern, the second pad pattern and a first anti-reflective pattern in the I/O region.

A method of manufacturing an image sensor, the method comprising:

• forming a plurality of photodiodes in a semiconductor layer in an active pixel region and a peripheral region;
• sequentially forming an insulating interlayer and a wiring structure on a first surface of the semiconductor layer in the active pixel region, the peripheral region and an input/output (I/O) region;
• forming a via hole through the semiconductor layer and the insulating interlayer to expose the wiring structure;
• sequentially forming a first metal layer and a second metal layer on a second surface of the semiconductor layer and the via hole, the second surface being opposite the first surface;
• patterning the second metal layer to form a second pad pattern in the I/O region, and to expose the first metal layer in the active pixel region and the peripheral region;
• forming an anti-reflective layer on the first metal layer and the second pad pattern;
• and
• patterning the anti-reflective layer and the first metal layer to form a light blocking structure including the first metal layer and the anti-reflective layer in the peripheral region, a pad structure including a via contact, a first pad pattern, the second pad pattern and a first anti-reflective pattern in the I/O region, and a grid structure including a first metal pattern and a second anti-reflective pattern stacked between unit pixels in the active pixel region.