Memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung Hwan SON, Won Chul JANG, Dong Seog EUN, Jae Hoon JANG
Life of this patent
Estimating the term…
Abstract
A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of vertical holes extending in a direction perpendicular to the upper surface of the substrate to penetrate through the gate structure, and a plurality of vertical structures in the plurality of vertical holes, respectively, each vertical structure of the plurality of vertical structures including an embedded insulating layer, and a plurality of channel layers separated from each other, the plurality of channel layers being outside the embedded insulating layer.
Claims20
A memory device, comprising:
- a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate;
- a plurality of vertical holes extending in a direction perpendicular to the upper surface of the substrate to penetrate through the gate structure;
- and
- a plurality of vertical structures in the plurality of vertical holes, respectively, each vertical structure of the plurality of vertical structures including an embedded insulating layer, and a plurality of channel layers separated from each other, the plurality of channel layers being outside the embedded insulating layer.
A memory device, comprising:
- a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate;
- an interlayer insulating layer on an upper surface of the gate structure;
- a plurality of vertical structures penetrating through the interlayer insulating layer and the gate structure, each of the vertical structures including an embedded insulating layer and a plurality of channel layers outside the embedded insulating layer;
- a plurality of studs directly connected to the plurality of channel layers in one of the plurality of vertical structures, respectively;
- and
- a plurality of bit lines connected to at least one of the plurality of studs.
A memory device, comprising:
- a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate;
- a plurality of vertical holes extending in a direction perpendicular to the upper surface of the substrate to penetrate through the gate structure;
- and
- a plurality of vertical structures in the plurality of vertical holes, respectively, each vertical structure of the plurality of vertical structures including a plurality of channel layers separated from each other by an embedded insulating layer within a same vertical hole.
Dependencies are inferred from the claim text.