US 2018/0019256 A1 · SELECTIVE TUNGSTEN GROWTH FOR WORD LINES OF A THREE-DIMENSIONAL MEMORY DEVICE

Abstract

Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.

Claims27

Dependent claims

A three-dimensional memory device comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory stack structures extending through the alternating stack, each of the memory stack structures including a memory material layer, a tunneling dielectric, and a vertical semiconductor channel;
a pair of backside trenches extending through the alternating stack and including respective backside contact via structures contacting a respective portion of the substrate;
metallic liner layers laterally extending between the pair of backside trenches;
and
polycrystalline aluminum oxide liners located between a respective metallic liner layer and a respective electrically conductive layer and laterally spaced from each of the pair of backside trenches by a respective lateral offset distance.

3 more elements

A method of forming a memory device, comprising:

forming an alternating stack of insulating material layers and sacrificial material layers over a substrate;
forming memory stack structures through the alternating stack;
forming a pair of backside trenches through the alternating stack;
forming backside recesses by removing the sacrificial material layers from the alternating stack;
depositing a metallic liner layer in the backside recesses and the pair of backside trenches;
forming tungsten nucleation layers in portions of the backside recesses that are laterally spaced from the pair of backside trenches by more than a lateral offset distance, while the metallic liner layer is physically exposed in portions of the backside recesses that are laterally offset from the backside trenches by less than the lateral offset distance;
and
selectively forming tungsten electrically conductive layers in the backside recesses using the tungsten nucleation layers.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/332,429Filed 24 Oct 2016

Priority

13 Jul 2016

Published

18 Jan 2018

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout
H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND
H10W 20/035
In openings in dielectrics: combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers

Selective tungsten growth for word lines of a three-dimensional memory device

Life of this patent

Selective tungsten growth for word lines of a three-dimensional memory device

Life of this patent

Abstract

Claims27