Elevationally-Extending String Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor And Method Of Forming An Elevationally-Extending String Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor

An elevationally-extending string of memory cells individually comprising a programmable charge storage transistor, comprising:

• an upper stack elevationally over a lower stack, the upper and lower stacks individually comprising vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material;
• an upper stack channel pillar extending through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extending through multiple of the vertically-alternating tiers in the lower stack;
• tunnel insulator, charge storage material, and control gate blocking insulator being laterally between the respective upper and lower stack channel pillars and the control gate material;
• and
• a conductive interconnect comprising conductively-doped semiconductor material elevationally between and electrically coupling the upper and lower stack channel pillars together, the conductively-doped semiconductor material comprising a first conductivity-producing dopant, the conductive interconnect comprising a lower half thereof having a conductive region comprising at least one of (a) conductive material below the conductively-doped semiconductor material, or (b) a second non-p-type dopant within the conductively-doped semiconductor material that is different from the first dopant, the second dopant being present at an atomic concentration within the semiconductor material of at least 0.1%.

An elevationally-extending string of memory cells individually comprising a programmable charge storage transistor, comprising:

• an upper stack elevationally over a lower stack, the upper and lower stacks individually comprising vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material;
• an upper stack p-type channel pillar extending through multiple of the vertically-alternating tiers in the upper stack and a lower stack p-type channel pillar extending through multiple of the vertically-alternating tiers in the lower stack;
• tunnel insulator, charge storage material, and control gate blocking insulator being laterally between the respective upper and lower stack p-type channel pillars and the control gate material;
• a conductive interconnect comprising conductively-doped n-type semiconductor material elevationally between and electrically coupling the upper and lower stack p-type channel pillars together, the conductively-doped n-type semiconductor material comprising a first n-type conductivity-producing dopant;
• and
• an upper region of the lower stack p-type channel pillar comprising a second non-p-type dopant that is different from the first n-type dopant, the second dopant being present in the upper region of the lower stack p-type channel pillar at an atomic concentration in the upper region of at least 0.1%.

An elevationally-extending string of memory cells individually comprising a programmable charge storage transistor, comprising:

• an upper stack elevationally over a lower stack, the upper and lower stacks individually comprising vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material;
• an upper stack channel pillar extending through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extending through multiple of the vertically-alternating tiers in the lower stack;
• tunnel insulator, charge storage material, and control gate blocking insulator being laterally between the respective upper and lower stack channel pillars and the control gate material;
• the upper and lower channel pillars comprising a channel conductivity-modifying dopant in a quantity that produces intrinsic semiconductor properties enabling the upper and lower channel pillars to operably function as switchable “on” and “off” channels for the individual memory cells for control gate voltage above and below, respectively, a Vt depending on programming state of the charge storage transistor for the respective individual memory cell;
• a conductive interconnect comprising conductively-doped semiconductor material elevationally between and electrically coupling the upper and lower stack channel pillars together, the conductively-doped semiconductor material comprising a first conductivity-producing dopant;
• and
• an upper region of the lower stack channel pillar comprising a second non-p-type dopant that is different from the first dopant and is different from the channel conductivity-modifying dopant, the second dopant being present in the upper region of the lower stack channel pillar at an atomic concentration in the upper region of at least 0.1%.

A method of forming an elevationally-extending string of memory cells individually comprising a programmable charge storage transistor, comprising:

• forming an upper stack elevationally over a lower stack, the upper and lower stacks individually comprising vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material, the upper stack comprising an upper stack channel pillar extending through multiple of the vertically-alternating tiers in the upper stack, the lower stack comprising a lower stack channel pillar extending through multiple of the vertically-alternating tiers in the lower stack, a conductive interconnect comprising conductively-doped semiconductor material elevationally between and electrically coupling the upper and lower stack channel pillars together, the conductively-doped semiconductor material comprising conductivity-producing dopant therein;
• thermally diffusing some of the conductivity-producing dopant elevationally out of the conductively-doped semiconductor material;
• using an asymmetric diffusion barrier during the thermally diffusing to thermally diffuse more of said dopant upwardly into the upper stack channel pillar than diffusion of said dopant, if any, into the lower stack channel pillar;
• and
• providing tunnel insulator, charge storage material, and control gate blocking insulator laterally between the respective upper and lower stack channel pillars and the control gate material.