Nonvolatile memory and fabrication method thereof
AssigneeeMemory Technology Inc.
InventorsChun-Hsiao Li, Wei-Ren Chen, Wein-Town Sun
Life of this patent
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Abstract
A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region for forming an erase gate region, and a trench isolation region separating the first OD region from the second OD region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is disposed on the first OD region. The floating gate transistor comprises a floating gate overlying the first OD region. A floating gate extension continuously extends from the floating gate to the second OD region. A shallow junction diffusion region is situated directly under the floating gate extension within the second OD region.
Claims19
A nonvolatile memory (NVM) cell, comprising:
- a semiconductor substrate of a first conductivity type;
- a first oxide define (OD) region in the semiconductor substrate;
- a second oxide define (OD) region for forming an erase gate (EG) region being spaced apart from the first OD region;
- a trench isolation region separating the first OD region from the second OD region;
- a select transistor disposed on the first OD region;
- a floating gate transistor serially connected to the select transistor and being disposed on the first OD region, wherein the floating gate transistor comprises a floating gate overlying the first OD region;
- a floating gate extension continuously extending from the floating gate to the second OD region;
- and
- a shallow junction diffusion region of a second conductivity type situated directly under the floating gate extension within the second OD region.
A method for forming a diffusion region in an erase gate region of a memory device, comprising:
- providing a semiconductor substrate having thereon a logic circuit region and a memory cell region, wherein the logic circuit region comprises an oxide define (OD) region for P type core device with regular threshold voltages, and an oxide define (OD) region for P type core device with high threshold voltages, wherein the memory cell region comprises an oxide define (OD) region for forming the erase gate region;
- and
- subjecting the OD region for P type core device with regular threshold voltages, the OD region for P type core device with high threshold voltages, and the OD region for forming the erase gate region to a first threshold voltage adjustment implant, thereby forming a first N type doping region therein and/or subjecting the OD region for P type core device with high threshold voltages, and the OD region for forming the erase gate region to a second threshold voltage adjustment implant, thereby forming a second N type doping region therein.
Dependencies are inferred from the claim text.