Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor device including a non-volatile memory area and a logic circuit area, the method comprising:

• forming a first and a second stacked structure of a non-volatile memory over the non-volatile memory area of a substrate;
• forming a conductive material layer over the first and second stacked structures and over the logic circuit area of the substrate;
• forming a planarization layer over the conductive material layer;
• forming a first mask pattern on the planarization layer over the non-volatile memory area and a second mask pattern on the planarization layer over the logic circuit area;
• patterning the planarization layer by using the first and second mask patterns as an etching mask;
• and
• patterning the conductive material layer, thereby forming an erase gate line between the first and second stacked structure and a first and a second word line in the non-volatile memory area, such that the first word line, the first stacked structure, the erase gate line, the second stacked structure and the second word line are arranged in this order along a direction parallel to a principal surface of the substrate, and forming a gate pattern in the logic circuit area,
• the first mask pattern includes a first-first mask pattern and a second-first mask pattern, and
• the first-first mask pattern is formed above a region where the first word line is to be formed, and the second-first mask pattern is formed above a region where the second word line is to be formed.

A method of manufacturing a semiconductor device including a non-volatile memory area and a logic circuit area, the method comprising:

• forming a first and a second stacked structure of a non-volatile memory over the non-volatile memory area of a substrate;
• forming a polysilicon layer over the first and second stacked structures and over the logic circuit area of the substrate;
• forming a planarization layer over the polysilicon layer;
• forming a mask pattern on the planarization layer over the logic circuit area;
• patterning the planarization layer by using the mask pattern as an etching mask;
• and
• patterning the polysilicon layer, thereby forming a gate pattern in the logic circuit area, wherein:
• the planarization layer includes a bottom layer and an upper layer thinner than the bottom layer, and
• the bottom layer is formed to cover the polysilicon layer.